| .. | .. |
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| 865 | 865 | struct imx327 *imx327 = to_imx327(sd); |
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| 866 | 866 | const struct imx327_mode *mode = imx327->cur_mode; |
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| 867 | 867 | |
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| 868 | | - mutex_lock(&imx327->mutex); |
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| 869 | 868 | fi->interval = mode->max_fps; |
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| 870 | | - mutex_unlock(&imx327->mutex); |
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| 871 | 869 | |
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| 872 | 870 | return 0; |
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| 873 | 871 | } |
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| 874 | 872 | |
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| 875 | | -static int imx327_g_mbus_config(struct v4l2_subdev *sd, |
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| 873 | +static int imx327_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, |
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| 876 | 874 | struct v4l2_mbus_config *config) |
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| 877 | 875 | { |
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| 878 | 876 | struct imx327 *imx327 = to_imx327(sd); |
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| .. | .. |
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| 881 | 879 | val = 1 << (IMX327_4LANES - 1) | |
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| 882 | 880 | V4L2_MBUS_CSI2_CHANNEL_0 | |
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| 883 | 881 | V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; |
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| 884 | | - if (imx327->bus_cfg.bus_type == 3) |
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| 885 | | - config->type = V4L2_MBUS_CCP2; |
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| 886 | | - else |
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| 887 | | - config->type = V4L2_MBUS_CSI2; |
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| 882 | + config->type = imx327->bus_cfg.bus_type; |
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| 888 | 883 | config->flags = val; |
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| 889 | 884 | |
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| 890 | 885 | return 0; |
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| .. | .. |
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| 1145 | 1140 | break; |
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| 1146 | 1141 | case RKMODULE_GET_LVDS_CFG: |
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| 1147 | 1142 | lvds_cfg = (struct rkmodule_lvds_cfg *)arg; |
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| 1148 | | - if (imx327->bus_cfg.bus_type == 3) |
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| 1143 | + if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) |
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| 1149 | 1144 | memcpy(lvds_cfg, &imx327->cur_mode->lvds_cfg, |
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| 1150 | 1145 | sizeof(struct rkmodule_lvds_cfg)); |
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| 1151 | 1146 | else |
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| .. | .. |
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| 1558 | 1553 | if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) { |
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| 1559 | 1554 | sel->r.left = CROP_START(imx327->cur_mode->width, DST_WIDTH); |
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| 1560 | 1555 | sel->r.width = DST_WIDTH; |
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| 1561 | | - if (imx327->bus_cfg.bus_type == 3) { |
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| 1556 | + if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) { |
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| 1562 | 1557 | if (imx327->cur_mode->hdr_mode == NO_HDR) |
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| 1563 | 1558 | sel->r.top = 21; |
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| 1564 | 1559 | else |
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| .. | .. |
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| 1594 | 1589 | static const struct v4l2_subdev_video_ops imx327_video_ops = { |
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| 1595 | 1590 | .s_stream = imx327_s_stream, |
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| 1596 | 1591 | .g_frame_interval = imx327_g_frame_interval, |
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| 1597 | | - .g_mbus_config = imx327_g_mbus_config, |
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| 1598 | 1592 | }; |
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| 1599 | 1593 | |
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| 1600 | 1594 | static const struct v4l2_subdev_pad_ops imx327_pad_ops = { |
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| .. | .. |
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| 1604 | 1598 | .get_fmt = imx327_get_fmt, |
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| 1605 | 1599 | .set_fmt = imx327_set_fmt, |
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| 1606 | 1600 | .get_selection = imx327_get_selection, |
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| 1601 | + .get_mbus_config = imx327_g_mbus_config, |
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| 1607 | 1602 | }; |
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| 1608 | 1603 | |
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| 1609 | 1604 | static const struct v4l2_subdev_ops imx327_subdev_ops = { |
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| .. | .. |
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| 1640 | 1635 | |
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| 1641 | 1636 | switch (ctrl->id) { |
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| 1642 | 1637 | case V4L2_CID_EXPOSURE: |
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| 1643 | | - shs1 = imx327->cur_vts - ctrl->val - 1; |
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| 1644 | | - ret = imx327_write_reg(imx327->client, |
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| 1645 | | - IMX327_REG_SHS1_H, |
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| 1646 | | - IMX327_REG_VALUE_08BIT, |
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| 1647 | | - IMX327_FETCH_HIGH_BYTE_EXP(shs1)); |
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| 1648 | | - ret |= imx327_write_reg(imx327->client, |
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| 1649 | | - IMX327_REG_SHS1_M, |
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| 1650 | | - IMX327_REG_VALUE_08BIT, |
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| 1651 | | - IMX327_FETCH_MID_BYTE_EXP(shs1)); |
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| 1652 | | - ret |= imx327_write_reg(imx327->client, |
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| 1653 | | - IMX327_REG_SHS1_L, |
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| 1654 | | - IMX327_REG_VALUE_08BIT, |
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| 1655 | | - IMX327_FETCH_LOW_BYTE_EXP(shs1)); |
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| 1656 | | - dev_dbg(&client->dev, "set exposure 0x%x, cur_vts 0x%x,shs1 0x%x\n", |
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| 1657 | | - ctrl->val, imx327->cur_vts, shs1); |
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| 1638 | + if (imx327->cur_mode->hdr_mode == NO_HDR) { |
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| 1639 | + shs1 = imx327->cur_vts - ctrl->val - 1; |
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| 1640 | + ret = imx327_write_reg(imx327->client, |
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| 1641 | + IMX327_REG_SHS1_H, |
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| 1642 | + IMX327_REG_VALUE_08BIT, |
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| 1643 | + IMX327_FETCH_HIGH_BYTE_EXP(shs1)); |
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| 1644 | + ret |= imx327_write_reg(imx327->client, |
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| 1645 | + IMX327_REG_SHS1_M, |
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| 1646 | + IMX327_REG_VALUE_08BIT, |
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| 1647 | + IMX327_FETCH_MID_BYTE_EXP(shs1)); |
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| 1648 | + ret |= imx327_write_reg(imx327->client, |
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| 1649 | + IMX327_REG_SHS1_L, |
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| 1650 | + IMX327_REG_VALUE_08BIT, |
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| 1651 | + IMX327_FETCH_LOW_BYTE_EXP(shs1)); |
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| 1652 | + dev_dbg(&client->dev, "set exposure 0x%x, cur_vts 0x%x,shs1 0x%x\n", |
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| 1653 | + ctrl->val, imx327->cur_vts, shs1); |
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| 1654 | + } |
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| 1658 | 1655 | break; |
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| 1659 | 1656 | case V4L2_CID_ANALOGUE_GAIN: |
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| 1660 | | - ret = imx327_write_reg(imx327->client, |
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| 1661 | | - IMX327_REG_LF_GAIN, |
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| 1662 | | - IMX327_REG_VALUE_08BIT, |
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| 1663 | | - ctrl->val); |
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| 1664 | | - dev_dbg(&client->dev, "set analog gain 0x%x\n", |
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| 1665 | | - ctrl->val); |
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| 1657 | + if (imx327->cur_mode->hdr_mode == NO_HDR) { |
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| 1658 | + ret = imx327_write_reg(imx327->client, |
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| 1659 | + IMX327_REG_LF_GAIN, |
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| 1660 | + IMX327_REG_VALUE_08BIT, |
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| 1661 | + ctrl->val); |
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| 1662 | + dev_dbg(&client->dev, "set analog gain 0x%x\n", |
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| 1663 | + ctrl->val); |
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| 1664 | + } |
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| 1666 | 1665 | break; |
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| 1667 | 1666 | case V4L2_CID_VBLANK: |
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| 1668 | 1667 | vts = ctrl->val + imx327->cur_mode->height; |
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| .. | .. |
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| 1893 | 1892 | |
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| 1894 | 1893 | ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), |
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| 1895 | 1894 | &imx327->bus_cfg); |
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| 1896 | | - if (imx327->bus_cfg.bus_type == 3) { |
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| 1895 | + if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) { |
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| 1897 | 1896 | imx327->support_modes = lvds_supported_modes; |
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| 1898 | 1897 | imx327->support_modes_num = ARRAY_SIZE(lvds_supported_modes); |
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| 1899 | 1898 | } else { |
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