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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/media/i2c/gc2093.c
....@@ -11,8 +11,6 @@
1111  * 2. add hdr mode exposure limit issue.
1212  * 3. fix hdr mode highlighting pink issue.
1313  * 4. add some debug info.
14
- * V0.0X01.0X03 fix hdr mode not support vts change
15
- * V0.0X01.0X04 add 24M MCLK register setting.
1614  */
1715 //#define DEBUG
1816 #include <linux/clk.h>
....@@ -34,22 +32,17 @@
3432 #include <media/v4l2-device.h>
3533 #include <media/v4l2-fwnode.h>
3634 #include <media/v4l2-subdev.h>
35
+#include "../platform/rockchip/isp/rkisp_tb_helper.h"
36
+#include "cam-tb-setup.h"
3737 
38
-#define DRIVER_VERSION		KERNEL_VERSION(0, 0x01, 0x04)
38
+#define DRIVER_VERSION		KERNEL_VERSION(0, 0x01, 0x02)
3939 #define GC2093_NAME		"gc2093"
4040 #define GC2093_MEDIA_BUS_FMT	MEDIA_BUS_FMT_SRGGB10_1X10
4141 
4242 #define MIPI_FREQ_297M		297000000
4343 #define MIPI_FREQ_396M		396000000
4444 
45
-/* 27M or 24M */
46
-#define MCLK_27M
47
-
48
-#ifdef MCLK_27M
4945 #define GC2093_XVCLK_FREQ	27000000
50
-#else
51
-#define GC2093_XVCLK_FREQ	24000000
52
-#endif
5346 
5447 #define GC2093_REG_CHIP_ID_H	0x03F0
5548 #define GC2093_REG_CHIP_ID_L	0x03F1
....@@ -90,6 +83,8 @@
9083 
9184 #define GC2093_LANES		2
9285 
86
+#define OF_CAMERA_HDR_MODE		"rockchip,camera-hdr-mode"
87
+
9388 static const char * const gc2093_supply_names[] = {
9489 	"dovdd",    /* Digital I/O power */
9590 	"avdd",     /* Analog power */
....@@ -99,14 +94,6 @@
9994 #define GC2093_NUM_SUPPLIES ARRAY_SIZE(gc2093_supply_names)
10095 
10196 #define to_gc2093(sd) container_of(sd, struct gc2093, subdev)
102
-
103
-enum {
104
-	PAD0,
105
-	PAD1,
106
-	PAD2,
107
-	PAD3,
108
-	PAD_MAX,
109
-};
11097 
11198 enum {
11299 	LINK_FREQ_297M_INDEX,
....@@ -158,16 +145,19 @@
158145 	struct mutex        lock;
159146 	bool		    streaming;
160147 	bool		    power_on;
161
-	unsigned int        cfg_num;
162148 	const struct gc2093_mode *cur_mode;
163149 
164150 	u32		module_index;
165151 	const char      *module_facing;
166152 	const char      *module_name;
167153 	const char      *len_name;
168
-	u32		cur_vts;
169154 
170
-	bool			  has_init_exp;
155
+	struct v4l2_fract	cur_fps;
156
+	u32			cur_vts;
157
+
158
+	bool			has_init_exp;
159
+	bool			is_thunderboot;
160
+	bool			is_first_streamoff;
171161 	struct preisp_hdrae_exp_s init_hdrae_exp;
172162 };
173163 
....@@ -189,7 +179,6 @@
189179  * row_time=29.62us frame_rate=30fps
190180  */
191181 static const struct reg_sequence gc2093_1080p_liner_settings[] = {
192
-#ifdef MCLK_27M
193182 	/* System */
194183 	{0x03fe, 0x80},
195184 	{0x03fe, 0x80},
....@@ -300,157 +289,6 @@
300289 	{0x0212, 0x80},
301290 	{0x0213, 0x07},
302291 	{0x003e, 0x91},
303
-#else
304
-	/****system****/
305
-	{0x03fe, 0xf0},
306
-	{0x03fe, 0xf0},
307
-	{0x03fe, 0xf0},
308
-	{0x03fe, 0x00},
309
-	{0x03f2, 0x00},
310
-	{0x03f3, 0x00},
311
-	{0x03f4, 0x36},
312
-	{0x03f5, 0xc0},
313
-	{0x03f6, 0x0B},
314
-	{0x03f7, 0x11},
315
-	{0x03f8, 0x30},
316
-	{0x03f9, 0x42},
317
-	{0x03fc, 0x8e},
318
-	/****CISCTL & ANALOG****/
319
-	{0x0087, 0x18},
320
-	{0x00ee, 0x30},
321
-	{0x00d0, 0xbf},
322
-	{0x01a0, 0x00},
323
-	{0x01a4, 0x40},
324
-	{0x01a5, 0x40},
325
-	{0x01a6, 0x40},
326
-	{0x01af, 0x09},
327
-	{0x0003, 0x04},
328
-	{0x0004, 0x65},
329
-	{0x0005, 0x05},
330
-	{0x0006, 0x8e},
331
-	{0x0007, 0x00},
332
-	{0x0008, 0x11},
333
-	{0x0009, 0x00},
334
-	{0x000a, 0x02},
335
-	{0x000b, 0x00},
336
-	{0x000c, 0x04},
337
-	{0x000d, 0x04},
338
-	{0x000e, 0x40},
339
-	{0x000f, 0x07},
340
-	{0x0010, 0x8c},
341
-	{0x0013, 0x15},
342
-	{0x0019, 0x0c},
343
-	{0x0041, 0x04},
344
-	{0x0042, 0x65},
345
-	{0x0053, 0x60},
346
-	{0x008d, 0x92},
347
-	{0x0090, 0x00},
348
-	{0x00c7, 0xe1},
349
-	{0x001b, 0x73},
350
-	{0x0028, 0x0d},
351
-	{0x0029, 0x40},
352
-	{0x002b, 0x04},
353
-	{0x002e, 0x23},
354
-	{0x0037, 0x03},
355
-	{0x0043, 0x04},
356
-	{0x0044, 0x30},
357
-	{0x004a, 0x01},
358
-	{0x004b, 0x28},
359
-	{0x0055, 0x30},
360
-	{0x0066, 0x3f},
361
-	{0x0068, 0x3f},
362
-	{0x006b, 0x44},
363
-	{0x0077, 0x00},
364
-	{0x0078, 0x20},
365
-	{0x007c, 0xa1},
366
-	{0x00ce, 0x7c},
367
-	{0x00d3, 0xd4},
368
-	{0x00e6, 0x50},
369
-	/*gain*/
370
-	{0x00b6, 0xc0},
371
-	{0x00b0, 0x68},
372
-	{0x00b3, 0x00},
373
-	{0x00b8, 0x01},
374
-	{0x00b9, 0x00},
375
-	{0x00b1, 0x01},
376
-	{0x00b2, 0x00},
377
-	/*isp*/
378
-	{0x0101, 0x0c},
379
-	{0x0102, 0x89},
380
-	{0x0104, 0x01},
381
-	{0x0107, 0xa6},
382
-	{0x0108, 0xa9},
383
-	{0x0109, 0xa8},
384
-	{0x010a, 0xa7},
385
-	{0x010b, 0xff},
386
-	{0x010c, 0xff},
387
-	{0x010f, 0x00},
388
-	{0x0158, 0x00},
389
-	{0x0428, 0x86},
390
-	{0x0429, 0x86},
391
-	{0x042a, 0x86},
392
-	{0x042b, 0x68},
393
-	{0x042c, 0x68},
394
-	{0x042d, 0x68},
395
-	{0x042e, 0x68},
396
-	{0x042f, 0x68},
397
-	{0x0430, 0x4f},
398
-	{0x0431, 0x68},
399
-	{0x0432, 0x67},
400
-	{0x0433, 0x66},
401
-	{0x0434, 0x66},
402
-	{0x0435, 0x66},
403
-	{0x0436, 0x66},
404
-	{0x0437, 0x66},
405
-	{0x0438, 0x62},
406
-	{0x0439, 0x62},
407
-	{0x043a, 0x62},
408
-	{0x043b, 0x62},
409
-	{0x043c, 0x62},
410
-	{0x043d, 0x62},
411
-	{0x043e, 0x62},
412
-	{0x043f, 0x62},
413
-	/*dark sun*/
414
-	{0x0123, 0x08},
415
-	{0x0123, 0x00},
416
-	{0x0120, 0x01},
417
-	{0x0121, 0x04},
418
-	{0x0122, 0x65},
419
-	{0x0124, 0x03},
420
-	{0x0125, 0xff},
421
-	{0x001a, 0x8c},
422
-	{0x00c6, 0xe0},
423
-	/*blk*/
424
-	{0x0026, 0x30},
425
-	{0x0142, 0x00},
426
-	{0x0149, 0x1e},
427
-	{0x014a, 0x0f},
428
-	{0x014b, 0x00},
429
-	{0x0155, 0x07},
430
-	{0x0414, 0x78},
431
-	{0x0415, 0x78},
432
-	{0x0416, 0x78},
433
-	{0x0417, 0x78},
434
-	{0x04e0, 0x18},
435
-	/*window*/
436
-	{0x0192, 0x02},
437
-	{0x0194, 0x03},
438
-	{0x0195, 0x04},
439
-	{0x0196, 0x38},
440
-	{0x0197, 0x07},
441
-	{0x0198, 0x80},
442
-	/****DVP & MIPI****/
443
-	{0x019a, 0x06},
444
-	{0x007b, 0x2a},
445
-	{0x0023, 0x2d},
446
-	{0x0201, 0x27},
447
-	{0x0202, 0x56},
448
-	{0x0203, 0xb6},
449
-	{0x0212, 0x80},
450
-	{0x0213, 0x07},
451
-	{0x0215, 0x10},
452
-	{0x003e, 0x91},
453
-#endif
454292 };
455293 
456294 /*
....@@ -460,7 +298,6 @@
460298  * row_time=13.33us frame_rate=60fps
461299  */
462300 static const struct reg_sequence gc2093_1080p_hdr_settings[] = {
463
-#ifdef MCLK_27M
464301 	/* System */
465302 	{0x03fe, 0x80},
466303 	{0x03fe, 0x80},
....@@ -502,7 +339,139 @@
502339 	{0x0010, 0x8c},
503340 	{0x0013, 0x15},
504341 	{0x0019, 0x0c},
505
-	{0x0041, 0x05}, //30fps: 0x4e2;   25FPS: 0x5dc:  20FPS: 0x753
342
+	{0x0041, 0x04},
343
+	{0x0042, 0xe2},
344
+	{0x0053, 0x60},
345
+	{0x008d, 0x92},
346
+	{0x0090, 0x00},
347
+	{0x00c7, 0xe1},
348
+	{0x001b, 0x73},
349
+	{0x0028, 0x0d},
350
+	{0x0029, 0x24},
351
+	{0x002b, 0x04},
352
+	{0x002e, 0x23},
353
+	{0x0037, 0x03},
354
+	{0x0043, 0x04},
355
+	{0x0044, 0x20},
356
+	{0x004a, 0x01},
357
+	{0x004b, 0x20},
358
+	{0x0055, 0x30},
359
+	{0x006b, 0x44},
360
+	{0x0077, 0x00},
361
+	{0x0078, 0x20},
362
+	{0x007c, 0xa1},
363
+	{0x00d3, 0xd4},
364
+	{0x00e6, 0x50},
365
+	/* Gain */
366
+	{0x00b6, 0xc0},
367
+	{0x00b0, 0x60},
368
+	/* Isp */
369
+	{0x0102, 0x89},
370
+	{0x0104, 0x01},
371
+	{0x010e, 0x01},
372
+	{0x0158, 0x00},
373
+	{0x0183, 0x01},
374
+	{0x0187, 0x50},
375
+	/* Dark sun*/
376
+	{0x0123, 0x08},
377
+	{0x0123, 0x00},
378
+	{0x0120, 0x01},
379
+	{0x0121, 0x00},
380
+	{0x0122, 0x10},
381
+	{0x0124, 0x03},
382
+	{0x0125, 0xff},
383
+	{0x0126, 0x3c},
384
+	{0x001a, 0x8c},
385
+	{0x00c6, 0xe0},
386
+	/* Blk */
387
+	{0x0026, 0x30},
388
+	{0x0142, 0x00},
389
+	{0x0149, 0x1e},
390
+	{0x014a, 0x0f},
391
+	{0x014b, 0x00},
392
+	{0x0155, 0x00},
393
+	{0x0414, 0x78},
394
+	{0x0415, 0x78},
395
+	{0x0416, 0x78},
396
+	{0x0417, 0x78},
397
+	{0x0454, 0x78},
398
+	{0x0455, 0x78},
399
+	{0x0456, 0x78},
400
+	{0x0457, 0x78},
401
+	{0x04e0, 0x18},
402
+	/* Window */
403
+	{0x0192, 0x02},
404
+	{0x0194, 0x03},
405
+	{0x0195, 0x04},
406
+	{0x0196, 0x38},
407
+	{0x0197, 0x07},
408
+	{0x0198, 0x80},
409
+	/* MIPI */
410
+	{0x019a, 0x06},
411
+	{0x007b, 0x2a},
412
+	{0x0023, 0x2d},
413
+	{0x0201, 0x27},
414
+	{0x0202, 0x56},
415
+	{0x0203, 0xb6},
416
+	{0x0212, 0x80},
417
+	{0x0213, 0x07},
418
+	{0x0215, 0x12},
419
+	{0x003e, 0x91},
420
+	/* HDR En */
421
+	{0x0027, 0x71},
422
+	{0x0215, 0x92},
423
+	{0x024d, 0x01},
424
+};
425
+
426
+/*
427
+ * window size=1920*1080 mipi@2lane
428
+ * mclk=27M mipi_clk=792Mbps
429
+ * pixel_line_total=2640 line_frame_total=1500
430
+ * row_time=20us frame_rate=50fps
431
+ */
432
+static const struct reg_sequence gc2093_1080p_25fps_hdr_settings[] = {
433
+	/* System */
434
+	{0x03fe, 0x80},
435
+	{0x03fe, 0x80},
436
+	{0x03fe, 0x80},
437
+	{0x03fe, 0x00},
438
+	{0x03f2, 0x00},
439
+	{0x03f3, 0x00},
440
+	{0x03f4, 0x36},
441
+	{0x03f5, 0xc0},
442
+	{0x03f6, 0x0B},
443
+	{0x03f7, 0x01},
444
+	{0x03f8, 0x58},
445
+	{0x03f9, 0x40},
446
+	{0x03fc, 0x8e},
447
+	/* Cisctl & Analog */
448
+	{0x0087, 0x18},
449
+	{0x00ee, 0x30},
450
+	{0x00d0, 0xbf},
451
+	{0x01a0, 0x00},
452
+	{0x01a4, 0x40},
453
+	{0x01a5, 0x40},
454
+	{0x01a6, 0x40},
455
+	{0x01af, 0x09},
456
+	{0x0001, 0x00},
457
+	{0x0002, 0x02},
458
+	{0x0003, 0x04},
459
+	{0x0004, 0x02},
460
+	{0x0005, 0x02},
461
+	{0x0006, 0x94},
462
+	{0x0007, 0x00},
463
+	{0x0008, 0x11},
464
+	{0x0009, 0x00},
465
+	{0x000a, 0x02},
466
+	{0x000b, 0x00},
467
+	{0x000c, 0x04},
468
+	{0x000d, 0x04},
469
+	{0x000e, 0x40},
470
+	{0x000f, 0x07},
471
+	{0x0010, 0x8c},
472
+	{0x0013, 0x15},
473
+	{0x0019, 0x0c},
474
+	{0x0041, 0x05},
506475 	{0x0042, 0xdc},
507476 	{0x0053, 0x60},
508477 	{0x008d, 0x92},
....@@ -584,135 +553,6 @@
584553 	{0x0027, 0x71},
585554 	{0x0215, 0x92},
586555 	{0x024d, 0x01},
587
-#else
588
-	/****system****/
589
-	{0x03fe, 0xf0},
590
-	{0x03fe, 0xf0},
591
-	{0x03fe, 0xf0},
592
-	{0x03fe, 0x00},
593
-	{0x03f2, 0x00},
594
-	{0x03f3, 0x00},
595
-	{0x03f4, 0x36},
596
-	{0x03f5, 0xc0},
597
-	{0x03f6, 0x0B},
598
-	{0x03f7, 0x01},
599
-	{0x03f8, 0x63},
600
-	{0x03f9, 0x40},
601
-	{0x03fc, 0x8e},
602
-	/****CISCTL & ANALOG****/
603
-	{0x0087, 0x18},
604
-	{0x00ee, 0x30},
605
-	{0x00d0, 0xbf},
606
-	{0x01a0, 0x00},
607
-	{0x01a4, 0x40},
608
-	{0x01a5, 0x40},
609
-	{0x01a6, 0x40},
610
-	{0x01af, 0x09},
611
-	{0x0001, 0x00},
612
-	{0x0002, 0x02},
613
-	{0x0003, 0x04},
614
-	{0x0004, 0x02},
615
-	{0x0005, 0x02},
616
-	{0x0006, 0x94},
617
-	{0x0007, 0x00},
618
-	{0x0008, 0x11},
619
-	{0x0009, 0x00},
620
-	{0x000a, 0x02},
621
-	{0x000b, 0x00},
622
-	{0x000c, 0x04},
623
-	{0x000d, 0x04},
624
-	{0x000e, 0x40},
625
-	{0x000f, 0x07},
626
-	{0x0010, 0x8c},
627
-	{0x0013, 0x15},
628
-	{0x0019, 0x0c},
629
-	{0x0041, 0x05}, //30fps: 0x4e2;   25FPS: 0x5dc:  20FPS: 0x753
630
-	{0x0042, 0xdc},
631
-	{0x0053, 0x60},
632
-	{0x008d, 0x92},
633
-	{0x0090, 0x00},
634
-	{0x00c7, 0xe1},
635
-	{0x001b, 0x73},
636
-	{0x0028, 0x0d},
637
-	{0x0029, 0x24},
638
-	{0x002b, 0x04},
639
-	{0x002e, 0x23},
640
-	{0x0037, 0x03},
641
-	{0x0043, 0x04},
642
-	{0x0044, 0x28},
643
-	{0x004a, 0x01},
644
-	{0x004b, 0x20},
645
-	{0x0055, 0x28},
646
-	{0x0066, 0x3f},
647
-	{0x0068, 0x3f},
648
-	{0x006b, 0x44},
649
-	{0x0077, 0x00},
650
-	{0x0078, 0x20},
651
-	{0x007c, 0xa1},
652
-	{0x00ce, 0x7c},
653
-	{0x00d3, 0xd4},
654
-	{0x00e6, 0x50},
655
-	/*gain*/
656
-	{0x00b6, 0xc0},
657
-	{0x00b0, 0x68},
658
-	/*isp*/
659
-	{0x0101, 0x0c},
660
-	{0x0102, 0x89},
661
-	{0x0104, 0x01},
662
-	{0x010e, 0x01},
663
-	{0x010f, 0x00},
664
-	{0x0158, 0x00},
665
-	{0x0183, 0x01},
666
-	{0x0187, 0x50},
667
-	/*dark sun*/
668
-	{0x0123, 0x08},
669
-	{0x0123, 0x00},
670
-	{0x0120, 0x01},
671
-	{0x0121, 0x04},
672
-	{0x0122, 0xd8},
673
-	{0x0124, 0x03},
674
-	{0x0125, 0xff},
675
-	{0x001a, 0x8c},
676
-	{0x00c6, 0xe0},
677
-	/*blk*/
678
-	{0x0026, 0x30},
679
-	{0x0142, 0x00},
680
-	{0x0149, 0x1e},
681
-	{0x014a, 0x0f},
682
-	{0x014b, 0x00},
683
-	{0x0155, 0x07},
684
-	{0x0414, 0x78},
685
-	{0x0415, 0x78},
686
-	{0x0416, 0x78},
687
-	{0x0417, 0x78},
688
-	{0x0454, 0x78},
689
-	{0x0455, 0x78},
690
-	{0x0456, 0x78},
691
-	{0x0457, 0x78},
692
-	{0x04e0, 0x18},
693
-	/*window*/
694
-	{0x0192, 0x02},
695
-	{0x0194, 0x03},
696
-	{0x0195, 0x04},
697
-	{0x0196, 0x38},
698
-	{0x0197, 0x07},
699
-	{0x0198, 0x80},
700
-	/****DVP & MIPI****/
701
-	{0x019a, 0x06},
702
-	{0x007b, 0x2a},
703
-	{0x0023, 0x2d},
704
-	{0x0201, 0x27},
705
-	{0x0202, 0x56},
706
-	{0x0203, 0xb6}, //try 0xce or 0x8e
707
-	{0x0212, 0x80},
708
-	{0x0213, 0x07},
709
-	{0x0215, 0x10},
710
-	{0x003e, 0x91},
711
-	/****HDR EN****/
712
-	{0x0027, 0x71},
713
-	{0x0215, 0x92},
714
-	{0x024d, 0x01},
715
-#endif
716556 };
717557 
718558 static const struct gc2093_mode supported_modes[] = {
....@@ -737,14 +577,33 @@
737577 		.height = 1080,
738578 		.max_fps = {
739579 			.numerator = 10000,
580
+			.denominator = 300000,
581
+		},
582
+		.exp_def = 0x460,
583
+		.hts_def = 0xa50,
584
+		.vts_def = 0x4e2,
585
+		.link_freq_index = LINK_FREQ_396M_INDEX,
586
+		.reg_list = gc2093_1080p_hdr_settings,
587
+		.reg_num = ARRAY_SIZE(gc2093_1080p_hdr_settings),
588
+		.hdr_mode = HDR_X2,
589
+		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
590
+		.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
591
+		.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
592
+		.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
593
+	},
594
+	{
595
+		.width = 1920,
596
+		.height = 1080,
597
+		.max_fps = {
598
+			.numerator = 10000,
740599 			.denominator = 250000,
741600 		},
742601 		.exp_def = 0x460,
743602 		.hts_def = 0xa50,
744
-		.vts_def = 0x5dc,//30fps: 0x4e2;   25FPS: 0x5dc:  20FPS: 0x753
603
+		.vts_def = 0x5dc,
745604 		.link_freq_index = LINK_FREQ_396M_INDEX,
746
-		.reg_list = gc2093_1080p_hdr_settings,
747
-		.reg_num = ARRAY_SIZE(gc2093_1080p_hdr_settings),
605
+		.reg_list = gc2093_1080p_25fps_hdr_settings,
606
+		.reg_num = ARRAY_SIZE(gc2093_1080p_25fps_hdr_settings),
748607 		.hdr_mode = HDR_X2,
749608 		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
750609 		.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
....@@ -847,6 +706,14 @@
847706 	return ret;
848707 }
849708 
709
+static void gc2093_modify_fps_info(struct gc2093 *gc2093)
710
+{
711
+	const struct gc2093_mode *mode = gc2093->cur_mode;
712
+
713
+	gc2093->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
714
+				      gc2093->cur_vts;
715
+}
716
+
850717 static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl)
851718 {
852719 	struct gc2093 *gc2093 = container_of(ctrl->handler,
....@@ -871,6 +738,7 @@
871738 
872739 	switch (ctrl->id) {
873740 	case V4L2_CID_EXPOSURE:
741
+		dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
874742 		if (gc2093->cur_mode->hdr_mode != NO_HDR)
875743 			goto ctrl_end;
876744 		dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
....@@ -880,29 +748,36 @@
880748 					ctrl->val & 0xff);
881749 		break;
882750 	case V4L2_CID_ANALOGUE_GAIN:
751
+		dev_dbg(gc2093->dev, "set gain value 0x%x, mode: %d\n",
752
+				ctrl->val, gc2093->cur_mode->hdr_mode);
883753 		if (gc2093->cur_mode->hdr_mode != NO_HDR)
884754 			goto ctrl_end;
885755 		dev_dbg(gc2093->dev, "set gain value 0x%x\n", ctrl->val);
886756 		gc2093_set_gain(gc2093, ctrl->val);
887757 		break;
888758 	case V4L2_CID_VBLANK:
889
-		if (gc2093->cur_mode->hdr_mode != NO_HDR)
890
-			goto ctrl_end;
759
+		dev_dbg(gc2093->dev, "set blank value 0x%x\n", ctrl->val);
891760 		vts = gc2093->cur_mode->height + ctrl->val;
892761 		gc2093->cur_vts = vts;
893762 		ret = gc2093_write_reg(gc2093, GC2093_REG_VTS_H,
894763 				       (vts >> 8) & 0x3f);
895764 		ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L,
896765 					vts & 0xff);
766
+		if (!ret)
767
+			gc2093->cur_vts = ctrl->val + gc2093->cur_mode->height;
768
+		if (gc2093->cur_vts != gc2093->cur_mode->vts_def)
769
+			gc2093_modify_fps_info(gc2093);
897770 		dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val);
898771 		break;
899772 	case V4L2_CID_HFLIP:
900
-			regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
901
-					   MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
773
+		dev_dbg(gc2093->dev, "set hflip 0x%x\n", ctrl->val);
774
+		regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
775
+				   MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
902776 		break;
903777 	case V4L2_CID_VFLIP:
904
-			regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
905
-					   FLIP_MASK,  ctrl->val ? FLIP_MASK : 0);
778
+		dev_dbg(gc2093->dev, "set vflip 0x%x\n", ctrl->val);
779
+		regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
780
+				   FLIP_MASK,  ctrl->val ? FLIP_MASK : 0);
906781 		break;
907782 	default:
908783 		dev_warn(gc2093->dev, "%s Unhandled id:0x%x, val:0x%x\n",
....@@ -959,7 +834,7 @@
959834 					   h_blank, h_blank, 1, h_blank);
960835 	if (gc2093->hblank)
961836 		gc2093->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
962
-
837
+	gc2093->cur_fps = mode->max_fps;
963838 	vblank_def = mode->vts_def - mode->height;
964839 	gc2093->cur_vts = mode->vts_def;
965840 	gc2093->vblank = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
....@@ -992,6 +867,8 @@
992867 
993868 	gc2093->subdev.ctrl_handler = handler;
994869 	gc2093->has_init_exp = false;
870
+	gc2093->cur_vts = mode->vts_def;
871
+	gc2093->cur_fps = mode->max_fps;
995872 
996873 	return 0;
997874 
....@@ -1018,6 +895,9 @@
1018895 		return ret;
1019896 	}
1020897 
898
+	if (gc2093->is_thunderboot)
899
+		return 0;
900
+
1021901 	ret = regulator_bulk_enable(GC2093_NUM_SUPPLIES, gc2093->supplies);
1022902 	if (ret < 0) {
1023903 		dev_err(dev, "Failed to enable regulators\n");
....@@ -1025,14 +905,14 @@
1025905 	}
1026906 
1027907 	if (!IS_ERR(gc2093->reset_gpio))
1028
-		gpiod_set_value_cansleep(gc2093->reset_gpio, 1);
908
+		gpiod_direction_output(gc2093->reset_gpio, 1);
1029909 
1030910 	usleep_range(1000, 2000);
1031911 
1032912 	if (!IS_ERR(gc2093->pwdn_gpio))
1033
-		gpiod_set_value_cansleep(gc2093->pwdn_gpio, 1);
913
+		gpiod_direction_output(gc2093->pwdn_gpio, 1);
1034914 	if (!IS_ERR(gc2093->reset_gpio))
1035
-		gpiod_set_value_cansleep(gc2093->reset_gpio, 0);
915
+		gpiod_direction_output(gc2093->reset_gpio, 0);
1036916 
1037917 	usleep_range(10000, 20000);
1038918 
....@@ -1045,20 +925,35 @@
1045925 
1046926 static void __gc2093_power_off(struct gc2093 *gc2093)
1047927 {
928
+	clk_disable_unprepare(gc2093->xvclk);
929
+	if (gc2093->is_thunderboot) {
930
+		if (gc2093->is_first_streamoff) {
931
+			gc2093->is_thunderboot = false;
932
+			gc2093->is_first_streamoff = false;
933
+		} else {
934
+			return;
935
+		}
936
+	}
937
+
1048938 	if (!IS_ERR(gc2093->reset_gpio))
1049
-		gpiod_set_value_cansleep(gc2093->reset_gpio, 1);
939
+		gpiod_direction_output(gc2093->reset_gpio, 1);
1050940 	if (!IS_ERR(gc2093->pwdn_gpio))
1051
-		gpiod_set_value_cansleep(gc2093->pwdn_gpio, 0);
941
+		gpiod_direction_output(gc2093->pwdn_gpio, 0);
1052942 
1053943 	regulator_bulk_disable(GC2093_NUM_SUPPLIES, gc2093->supplies);
1054
-	clk_disable_unprepare(gc2093->xvclk);
1055944 }
1056945 
1057946 static int gc2093_check_sensor_id(struct gc2093 *gc2093)
1058947 {
948
+	struct device *dev = gc2093->dev;
1059949 	u8 id_h = 0, id_l = 0;
1060950 	u16 id = 0;
1061951 	int ret = 0;
952
+
953
+	if (gc2093->is_thunderboot) {
954
+		dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
955
+		return 0;
956
+	}
1062957 
1063958 	ret = gc2093_read_reg(gc2093, GC2093_REG_CHIP_ID_H, &id_h);
1064959 	ret |= gc2093_read_reg(gc2093, GC2093_REG_CHIP_ID_L, &id_l);
....@@ -1086,11 +981,24 @@
1086981 	strlcpy(inf->base.module, gc2093->module_name, sizeof(inf->base.module));
1087982 }
1088983 
984
+static int gc2093_get_channel_info(struct gc2093 *gc2093,
985
+				   struct rkmodule_channel_info *ch_info)
986
+{
987
+	if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
988
+		return -EINVAL;
989
+	ch_info->vc = gc2093->cur_mode->vc[ch_info->index];
990
+	ch_info->width = gc2093->cur_mode->width;
991
+	ch_info->height = gc2093->cur_mode->height;
992
+	ch_info->bus_fmt = GC2093_MEDIA_BUS_FMT;
993
+	return 0;
994
+}
995
+
1089996 static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1090997 {
1091998 	struct gc2093 *gc2093 = to_gc2093(sd);
1092999 	struct preisp_hdrae_exp_s *hdrae_exp = arg;
10931000 	struct rkmodule_hdr_cfg *hdr_cfg;
1001
+	struct rkmodule_channel_info *ch_info;
10941002 	long ret = 0;
10951003 	u32 i, h, w;
10961004 	u32 stream = 0;
....@@ -1107,8 +1015,7 @@
11071015 			dev_info(gc2093->dev, "don't streaming, record hdrae\n");
11081016 			break;
11091017 		}
1110
-		/* group hold start*/
1111
-		gc2093_write_reg(gc2093, 0x031d, 0x2c);
1018
+
11121019 		ret = gc2093_set_gain(gc2093, hdrae_exp->short_gain_reg);
11131020 		if (ret) {
11141021 			dev_err(gc2093->dev, "Failed to set gain!)\n");
....@@ -1171,8 +1078,6 @@
11711078 					(short_exp >> 8) & 0x3f);
11721079 		ret |= gc2093_write_reg(gc2093, GC2093_REG_EXP_SHORT_L,
11731080 					short_exp & 0xff);
1174
-		/* group hold end*/
1175
-		gc2093_write_reg(gc2093, 0x031d, 0x28);
11761081 		break;
11771082 	case RKMODULE_GET_HDR_CFG:
11781083 		hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
....@@ -1183,15 +1088,18 @@
11831088 		hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
11841089 		w = gc2093->cur_mode->width;
11851090 		h = gc2093->cur_mode->height;
1186
-		for (i = 0; i < gc2093->cfg_num; i++) {
1091
+		for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
11871092 			if (w == supported_modes[i].width &&
11881093 			h == supported_modes[i].height &&
11891094 			supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
11901095 				gc2093->cur_mode = &supported_modes[i];
11911096 				break;
11921097 			}
1098
+			dev_err(gc2093->dev, "i:%d,w:%d, h:%d, hdr:%d\n",
1099
+					i, supported_modes[i].width, supported_modes[i].height,
1100
+					supported_modes[i].hdr_mode);
11931101 		}
1194
-		if (i == gc2093->cfg_num) {
1102
+		if (i == ARRAY_SIZE(supported_modes)) {
11951103 			dev_err(gc2093->dev, "not find hdr mode:%d %dx%d config\n",
11961104 				hdr_cfg->hdr_mode, w, h);
11971105 			ret = -EINVAL;
....@@ -1203,6 +1111,7 @@
12031111 						 GC2093_VTS_MAX - gc2093->cur_mode->height,
12041112 						 1, h);
12051113 			gc2093->cur_vts = gc2093->cur_mode->vts_def;
1114
+			gc2093->cur_fps = gc2093->cur_mode->max_fps;
12061115 			dev_info(gc2093->dev, "sensor mode: %d\n",
12071116 				 gc2093->cur_mode->hdr_mode);
12081117 		}
....@@ -1226,6 +1135,10 @@
12261135 			usleep_range(delay_us, delay_us + 2000);
12271136 		}
12281137 		break;
1138
+	case RKMODULE_GET_CHANNEL_INFO:
1139
+		ch_info = (struct rkmodule_channel_info *)arg;
1140
+		ret = gc2093_get_channel_info(gc2093, ch_info);
1141
+		break;
12291142 	default:
12301143 		ret = -ENOIOCTLCMD;
12311144 		break;
....@@ -1237,33 +1150,46 @@
12371150 {
12381151 	int ret;
12391152 
1240
-	ret = regmap_multi_reg_write(gc2093->regmap,
1241
-				     gc2093->cur_mode->reg_list,
1242
-				     gc2093->cur_mode->reg_num);
1243
-	if (ret)
1244
-		return ret;
1245
-
1246
-	/* Apply customized control from user */
1247
-	mutex_unlock(&gc2093->lock);
1248
-	v4l2_ctrl_handler_setup(&gc2093->ctrl_handler);
1249
-	mutex_lock(&gc2093->lock);
1250
-
1251
-	if (gc2093->has_init_exp && gc2093->cur_mode->hdr_mode != NO_HDR) {
1252
-		ret = gc2093_ioctl(&gc2093->subdev, PREISP_CMD_SET_HDRAE_EXP,
1253
-				   &gc2093->init_hdrae_exp);
1254
-		if (ret) {
1255
-			dev_err(gc2093->dev, "init exp fail in hdr mode\n");
1153
+	if (!gc2093->is_thunderboot) {
1154
+		ret = regmap_multi_reg_write(gc2093->regmap,
1155
+						gc2093->cur_mode->reg_list,
1156
+						gc2093->cur_mode->reg_num);
1157
+		if (ret)
12561158 			return ret;
1159
+
1160
+		/* Apply customized control from user */
1161
+		mutex_unlock(&gc2093->lock);
1162
+		v4l2_ctrl_handler_setup(&gc2093->ctrl_handler);
1163
+		mutex_lock(&gc2093->lock);
1164
+
1165
+		if (gc2093->has_init_exp && gc2093->cur_mode->hdr_mode != NO_HDR) {
1166
+			ret = gc2093_ioctl(&gc2093->subdev, PREISP_CMD_SET_HDRAE_EXP,
1167
+					&gc2093->init_hdrae_exp);
1168
+			if (ret) {
1169
+				dev_err(gc2093->dev, "init exp fail in hdr mode\n");
1170
+				return ret;
1171
+			}
12571172 		}
12581173 	}
1259
-
1174
+	dev_info(gc2093->dev,
1175
+		 "%dx%d@%d, mode %d, vts 0x%x\n",
1176
+		 gc2093->cur_mode->width,
1177
+		 gc2093->cur_mode->height,
1178
+		 gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
1179
+		 gc2093->cur_mode->hdr_mode,
1180
+		 gc2093->cur_vts);
1181
+	dev_info(gc2093->dev, "is_tb:%d\n", gc2093->is_thunderboot);
12601182 	return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
1261
-				GC2093_MODE_STREAMING);
1183
+							GC2093_MODE_STREAMING);
12621184 }
12631185 
12641186 static int __gc2093_stop_stream(struct gc2093 *gc2093)
12651187 {
12661188 	gc2093->has_init_exp = false;
1189
+	if (gc2093->is_thunderboot) {
1190
+		gc2093->is_first_streamoff = true;
1191
+		pm_runtime_put(gc2093->dev);
1192
+	}
12671193 	return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
12681194 				GC2093_MODE_SW_STANDBY);
12691195 }
....@@ -1276,6 +1202,7 @@
12761202 	struct rkmodule_inf *inf;
12771203 	struct rkmodule_hdr_cfg *hdr;
12781204 	struct preisp_hdrae_exp_s *hdrae;
1205
+	struct rkmodule_channel_info *ch_info;
12791206 	long ret = 0;
12801207 	u32 stream = 0;
12811208 
....@@ -1345,6 +1272,21 @@
13451272 		else
13461273 			ret = -EFAULT;
13471274 		break;
1275
+	case RKMODULE_GET_CHANNEL_INFO:
1276
+		ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1277
+		if (!ch_info) {
1278
+			ret = -ENOMEM;
1279
+			return ret;
1280
+		}
1281
+
1282
+		ret = gc2093_ioctl(sd, cmd, ch_info);
1283
+		if (!ret) {
1284
+			ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1285
+			if (ret)
1286
+				ret = -EFAULT;
1287
+		}
1288
+		kfree(ch_info);
1289
+		break;
13481290 	default:
13491291 		ret = -ENOIOCTLCMD;
13501292 		break;
....@@ -1363,17 +1305,27 @@
13631305 	fps = DIV_ROUND_CLOSEST(gc2093->cur_mode->max_fps.denominator,
13641306 					gc2093->cur_mode->max_fps.numerator);
13651307 
1366
-	dev_info(gc2093->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1367
-				gc2093->cur_mode->width,
1368
-				gc2093->cur_mode->height,
1369
-				fps);
1308
+	dev_info(gc2093->dev,
1309
+		 "%dx%d@%d, mode %d, vts 0x%x\n",
1310
+		 gc2093->cur_mode->width,
1311
+		 gc2093->cur_mode->height,
1312
+		 gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
1313
+		 gc2093->cur_mode->hdr_mode,
1314
+		 gc2093->cur_vts);
13701315 
1316
+	dev_info(gc2093->dev,
1317
+		 "stream:%d\n, on:%d",
1318
+		 gc2093->streaming, on);
13711319 	mutex_lock(&gc2093->lock);
13721320 	on = !!on;
13731321 	if (on == gc2093->streaming)
13741322 		goto unlock_and_return;
13751323 
13761324 	if (on) {
1325
+		if (gc2093->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1326
+			gc2093->is_thunderboot = false;
1327
+			__gc2093_power_on(gc2093);
1328
+		}
13771329 		ret = pm_runtime_get_sync(gc2093->dev);
13781330 		if (ret < 0) {
13791331 			pm_runtime_put_noidle(gc2093->dev);
....@@ -1410,21 +1362,22 @@
14101362 	struct gc2093 *gc2093 = to_gc2093(sd);
14111363 	const struct gc2093_mode *mode = gc2093->cur_mode;
14121364 
1413
-	mutex_lock(&gc2093->lock);
1414
-	fi->interval = mode->max_fps;
1415
-	mutex_unlock(&gc2093->lock);
1365
+	if (gc2093->streaming)
1366
+		fi->interval = gc2093->cur_fps;
1367
+	else
1368
+		fi->interval = mode->max_fps;
14161369 
14171370 	return 0;
14181371 }
14191372 
1420
-static int gc2093_g_mbus_config(struct v4l2_subdev *sd,
1373
+static int gc2093_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
14211374 				struct v4l2_mbus_config *config)
14221375 {
14231376 	struct gc2093 *gc2093 = to_gc2093(sd);
14241377 	u32 val = 1 << (GC2093_LANES - 1) | V4L2_MBUS_CSI2_CHANNEL_0 |
14251378 		  V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
14261379 
1427
-	config->type = V4L2_MBUS_CSI2;
1380
+	config->type = V4L2_MBUS_CSI2_DPHY;
14281381 	config->flags = (gc2093->cur_mode->hdr_mode == NO_HDR) ?
14291382 			val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
14301383 
....@@ -1445,9 +1398,7 @@
14451398 				   struct v4l2_subdev_pad_config *cfg,
14461399 				   struct v4l2_subdev_frame_size_enum *fse)
14471400 {
1448
-	struct gc2093 *gc2093 = to_gc2093(sd);
1449
-
1450
-	if (fse->index >= gc2093->cfg_num)
1401
+	if (fse->index >= ARRAY_SIZE(supported_modes))
14511402 		return -EINVAL;
14521403 
14531404 	if (fse->code != GC2093_MEDIA_BUS_FMT)
....@@ -1464,9 +1415,7 @@
14641415 						  struct v4l2_subdev_pad_config *cfg,
14651416 						  struct v4l2_subdev_frame_interval_enum *fie)
14661417 {
1467
-	struct gc2093 *gc2093 = to_gc2093(sd);
1468
-
1469
-	if (fie->index >= gc2093->cfg_num)
1418
+	if (fie->index >= ARRAY_SIZE(supported_modes))
14701419 		return -EINVAL;
14711420 
14721421 	fie->code = GC2093_MEDIA_BUS_FMT;
....@@ -1515,6 +1464,8 @@
15151464 		__v4l2_ctrl_modify_range(gc2093->vblank, vblank_def,
15161465 					 GC2093_VTS_MAX - mode->height,
15171466 					 1, vblank_def);
1467
+		gc2093->cur_vts = mode->vts_def;
1468
+		gc2093->cur_fps = mode->max_fps;
15181469 	}
15191470 
15201471 	mutex_unlock(&gc2093->lock);
....@@ -1618,7 +1569,6 @@
16181569 static const struct v4l2_subdev_video_ops gc2093_video_ops = {
16191570 	.s_stream = gc2093_s_stream,
16201571 	.g_frame_interval = gc2093_g_frame_interval,
1621
-	.g_mbus_config = gc2093_g_mbus_config,
16221572 };
16231573 
16241574 static const struct v4l2_subdev_pad_ops gc2093_pad_ops = {
....@@ -1627,6 +1577,7 @@
16271577 	.enum_frame_interval = gc2093_enum_frame_interval,
16281578 	.get_fmt = gc2093_get_fmt,
16291579 	.set_fmt = gc2093_set_fmt,
1580
+	.get_mbus_config = gc2093_g_mbus_config,
16301581 };
16311582 
16321583 static const struct v4l2_subdev_ops gc2093_subdev_ops = {
....@@ -1635,7 +1586,7 @@
16351586 	.pad    = &gc2093_pad_ops,
16361587 };
16371588 
1638
-static int gc2093_runtime_resume(struct device *dev)
1589
+static int __maybe_unused gc2093_runtime_resume(struct device *dev)
16391590 {
16401591 	struct i2c_client *client = to_i2c_client(dev);
16411592 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
....@@ -1645,7 +1596,7 @@
16451596 	return 0;
16461597 }
16471598 
1648
-static int gc2093_runtime_suspend(struct device *dev)
1599
+static int __maybe_unused gc2093_runtime_suspend(struct device *dev)
16491600 {
16501601 	struct i2c_client *client = to_i2c_client(dev);
16511602 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
....@@ -1659,6 +1610,78 @@
16591610 	SET_RUNTIME_PM_OPS(gc2093_runtime_suspend,
16601611 			   gc2093_runtime_resume, NULL)
16611612 };
1613
+
1614
+
1615
+#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
1616
+static void find_terminal_resolution(struct gc2093 *gc2093)
1617
+{
1618
+	int i = 0;
1619
+	const struct gc2093_mode *mode = NULL;
1620
+	const struct gc2093_mode *fit_mode = NULL;
1621
+	u32 cur_fps = 0;
1622
+	u32 dst_fps = 0;
1623
+	u32 tmp_fps = 0;
1624
+	u32 rk_cam_hdr = get_rk_cam_hdr();
1625
+	u32 rk_cam_w = get_rk_cam_w();
1626
+	u32 rk_cam_h = get_rk_cam_h();
1627
+	u32 rk_cam_fps = get_rk_cam_fps();
1628
+
1629
+	if (rk_cam_w == 0 || rk_cam_h == 0 ||
1630
+	    rk_cam_fps == 0)
1631
+		goto err_find_res;
1632
+
1633
+	dev_info(gc2093->dev, "find resolution width: %d, height: %d, hdr: %d, fps: %d\n",
1634
+		 rk_cam_w, rk_cam_h, rk_cam_hdr, rk_cam_fps);
1635
+	dst_fps = rk_cam_fps;
1636
+	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1637
+		mode = &supported_modes[i];
1638
+		cur_fps = mode->max_fps.denominator / mode->max_fps.numerator;
1639
+		if (mode->width == rk_cam_w && mode->height == rk_cam_h &&
1640
+		    mode->hdr_mode == rk_cam_hdr) {
1641
+			if (cur_fps == dst_fps) {
1642
+				gc2093->cur_mode = mode;
1643
+				return;
1644
+			}
1645
+			if (cur_fps >= dst_fps) {
1646
+				if (fit_mode) {
1647
+					tmp_fps = fit_mode->max_fps.denominator /
1648
+							  fit_mode->max_fps.numerator;
1649
+					if (tmp_fps - dst_fps > cur_fps - dst_fps)
1650
+						fit_mode = mode;
1651
+				} else {
1652
+					fit_mode = mode;
1653
+				}
1654
+			}
1655
+		}
1656
+	}
1657
+	if (fit_mode) {
1658
+		gc2093->cur_mode = fit_mode;
1659
+		return;
1660
+	}
1661
+err_find_res:
1662
+	dev_err(gc2093->dev, "not match %dx%d@%dfps mode %d\n!",
1663
+		rk_cam_w, rk_cam_h, dst_fps, rk_cam_hdr);
1664
+	gc2093->cur_mode = &supported_modes[0];
1665
+}
1666
+#else
1667
+static void find_terminal_resolution(struct gc2093 *gc2093)
1668
+{
1669
+	u32 hdr_mode = 0;
1670
+	struct device_node *node = gc2093->dev->of_node;
1671
+	int i = 0;
1672
+
1673
+	of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1674
+	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1675
+		if (hdr_mode == supported_modes[i].hdr_mode) {
1676
+			gc2093->cur_mode = &supported_modes[i];
1677
+			break;
1678
+		}
1679
+	}
1680
+	if (i == ARRAY_SIZE(supported_modes))
1681
+		gc2093->cur_mode = &supported_modes[0];
1682
+
1683
+}
1684
+#endif
16621685 
16631686 static int gc2093_probe(struct i2c_client *client,
16641687 			 const struct i2c_device_id *id)
....@@ -1699,17 +1722,21 @@
16991722 		return -EINVAL;
17001723 	}
17011724 
1725
+	gc2093->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1726
+
17021727 	gc2093->xvclk = devm_clk_get(gc2093->dev, "xvclk");
17031728 	if (IS_ERR(gc2093->xvclk)) {
17041729 		dev_err(gc2093->dev, "Failed to get xvclk\n");
17051730 		return -EINVAL;
17061731 	}
17071732 
1708
-	gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1733
+	find_terminal_resolution(gc2093);
1734
+
1735
+	gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
17091736 	if (IS_ERR(gc2093->reset_gpio))
17101737 		dev_warn(dev, "Failed to get reset-gpios\n");
17111738 
1712
-	gc2093->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_HIGH);
1739
+	gc2093->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
17131740 	if (IS_ERR(gc2093->pwdn_gpio))
17141741 		dev_warn(dev, "Failed to get pwdn-gpios\n");
17151742 
....@@ -1720,11 +1747,6 @@
17201747 	}
17211748 
17221749 	mutex_init(&gc2093->lock);
1723
-
1724
-	/* set default mode */
1725
-	gc2093->cur_mode = &supported_modes[0];
1726
-	gc2093->cfg_num = ARRAY_SIZE(supported_modes);
1727
-	gc2093->cur_vts = gc2093->cur_mode->vts_def;
17281750 
17291751 	sd = &gc2093->subdev;
17301752 	v4l2_i2c_subdev_init(sd, client, &gc2093_subdev_ops);
....@@ -1771,7 +1793,10 @@
17711793 
17721794 	pm_runtime_set_active(dev);
17731795 	pm_runtime_enable(dev);
1774
-	pm_runtime_idle(dev);
1796
+	if (gc2093->is_thunderboot)
1797
+		pm_runtime_get_sync(dev);
1798
+	else
1799
+		pm_runtime_idle(dev);
17751800 
17761801 	return 0;
17771802 
....@@ -1839,7 +1864,11 @@
18391864 	i2c_del_driver(&gc2093_i2c_driver);
18401865 }
18411866 
1867
+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1868
+subsys_initcall(sensor_mod_init);
1869
+#else
18421870 device_initcall_sync(sensor_mod_init);
1871
+#endif
18431872 module_exit(sensor_mod_exit);
18441873 
18451874 MODULE_DESCRIPTION("Galaxycore GC2093 Image Sensor driver");