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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/media/i2c/gc2093.c
....@@ -33,6 +33,7 @@
3333 #include <media/v4l2-fwnode.h>
3434 #include <media/v4l2-subdev.h>
3535 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
36
+#include "cam-tb-setup.h"
3637 
3738 #define DRIVER_VERSION		KERNEL_VERSION(0, 0x01, 0x02)
3839 #define GC2093_NAME		"gc2093"
....@@ -81,6 +82,8 @@
8182 #define REG_NULL		0xFFFF
8283 
8384 #define GC2093_LANES		2
85
+
86
+#define OF_CAMERA_HDR_MODE		"rockchip,camera-hdr-mode"
8487 
8588 static const char * const gc2093_supply_names[] = {
8689 	"dovdd",    /* Digital I/O power */
....@@ -142,7 +145,6 @@
142145 	struct mutex        lock;
143146 	bool		    streaming;
144147 	bool		    power_on;
145
-	unsigned int        cfg_num;
146148 	const struct gc2093_mode *cur_mode;
147149 
148150 	u32		module_index;
....@@ -421,6 +423,138 @@
421423 	{0x024d, 0x01},
422424 };
423425 
426
+/*
427
+ * window size=1920*1080 mipi@2lane
428
+ * mclk=27M mipi_clk=792Mbps
429
+ * pixel_line_total=2640 line_frame_total=1500
430
+ * row_time=20us frame_rate=50fps
431
+ */
432
+static const struct reg_sequence gc2093_1080p_25fps_hdr_settings[] = {
433
+	/* System */
434
+	{0x03fe, 0x80},
435
+	{0x03fe, 0x80},
436
+	{0x03fe, 0x80},
437
+	{0x03fe, 0x00},
438
+	{0x03f2, 0x00},
439
+	{0x03f3, 0x00},
440
+	{0x03f4, 0x36},
441
+	{0x03f5, 0xc0},
442
+	{0x03f6, 0x0B},
443
+	{0x03f7, 0x01},
444
+	{0x03f8, 0x58},
445
+	{0x03f9, 0x40},
446
+	{0x03fc, 0x8e},
447
+	/* Cisctl & Analog */
448
+	{0x0087, 0x18},
449
+	{0x00ee, 0x30},
450
+	{0x00d0, 0xbf},
451
+	{0x01a0, 0x00},
452
+	{0x01a4, 0x40},
453
+	{0x01a5, 0x40},
454
+	{0x01a6, 0x40},
455
+	{0x01af, 0x09},
456
+	{0x0001, 0x00},
457
+	{0x0002, 0x02},
458
+	{0x0003, 0x04},
459
+	{0x0004, 0x02},
460
+	{0x0005, 0x02},
461
+	{0x0006, 0x94},
462
+	{0x0007, 0x00},
463
+	{0x0008, 0x11},
464
+	{0x0009, 0x00},
465
+	{0x000a, 0x02},
466
+	{0x000b, 0x00},
467
+	{0x000c, 0x04},
468
+	{0x000d, 0x04},
469
+	{0x000e, 0x40},
470
+	{0x000f, 0x07},
471
+	{0x0010, 0x8c},
472
+	{0x0013, 0x15},
473
+	{0x0019, 0x0c},
474
+	{0x0041, 0x05},
475
+	{0x0042, 0xdc},
476
+	{0x0053, 0x60},
477
+	{0x008d, 0x92},
478
+	{0x0090, 0x00},
479
+	{0x00c7, 0xe1},
480
+	{0x001b, 0x73},
481
+	{0x0028, 0x0d},
482
+	{0x0029, 0x24},
483
+	{0x002b, 0x04},
484
+	{0x002e, 0x23},
485
+	{0x0037, 0x03},
486
+	{0x0043, 0x04},
487
+	{0x0044, 0x20},
488
+	{0x004a, 0x01},
489
+	{0x004b, 0x20},
490
+	{0x0055, 0x30},
491
+	{0x006b, 0x44},
492
+	{0x0077, 0x00},
493
+	{0x0078, 0x20},
494
+	{0x007c, 0xa1},
495
+	{0x00d3, 0xd4},
496
+	{0x00e6, 0x50},
497
+	/* Gain */
498
+	{0x00b6, 0xc0},
499
+	{0x00b0, 0x60},
500
+	/* Isp */
501
+	{0x0102, 0x89},
502
+	{0x0104, 0x01},
503
+	{0x010e, 0x01},
504
+	{0x0158, 0x00},
505
+	{0x0183, 0x01},
506
+	{0x0187, 0x50},
507
+	/* Dark sun*/
508
+	{0x0123, 0x08},
509
+	{0x0123, 0x00},
510
+	{0x0120, 0x01},
511
+	{0x0121, 0x00},
512
+	{0x0122, 0x10},
513
+	{0x0124, 0x03},
514
+	{0x0125, 0xff},
515
+	{0x0126, 0x3c},
516
+	{0x001a, 0x8c},
517
+	{0x00c6, 0xe0},
518
+	/* Blk */
519
+	{0x0026, 0x30},
520
+	{0x0142, 0x00},
521
+	{0x0149, 0x1e},
522
+	{0x014a, 0x0f},
523
+	{0x014b, 0x00},
524
+	{0x0155, 0x00},
525
+	{0x0414, 0x78},
526
+	{0x0415, 0x78},
527
+	{0x0416, 0x78},
528
+	{0x0417, 0x78},
529
+	{0x0454, 0x78},
530
+	{0x0455, 0x78},
531
+	{0x0456, 0x78},
532
+	{0x0457, 0x78},
533
+	{0x04e0, 0x18},
534
+	/* Window */
535
+	{0x0192, 0x02},
536
+	{0x0194, 0x03},
537
+	{0x0195, 0x04},
538
+	{0x0196, 0x38},
539
+	{0x0197, 0x07},
540
+	{0x0198, 0x80},
541
+	/* MIPI */
542
+	{0x019a, 0x06},
543
+	{0x007b, 0x2a},
544
+	{0x0023, 0x2d},
545
+	{0x0201, 0x27},
546
+	{0x0202, 0x56},
547
+	{0x0203, 0xb6},
548
+	{0x0212, 0x80},
549
+	{0x0213, 0x07},
550
+	{0x0215, 0x12},
551
+	{0x003e, 0x91},
552
+	/* HDR En */
553
+	{0x0027, 0x71},
554
+	{0x0215, 0x92},
555
+	{0x024d, 0x01},
556
+};
557
+
424558 static const struct gc2093_mode supported_modes[] = {
425559 	{
426560 		.width = 1920,
....@@ -451,6 +585,25 @@
451585 		.link_freq_index = LINK_FREQ_396M_INDEX,
452586 		.reg_list = gc2093_1080p_hdr_settings,
453587 		.reg_num = ARRAY_SIZE(gc2093_1080p_hdr_settings),
588
+		.hdr_mode = HDR_X2,
589
+		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
590
+		.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
591
+		.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
592
+		.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
593
+	},
594
+	{
595
+		.width = 1920,
596
+		.height = 1080,
597
+		.max_fps = {
598
+			.numerator = 10000,
599
+			.denominator = 250000,
600
+		},
601
+		.exp_def = 0x460,
602
+		.hts_def = 0xa50,
603
+		.vts_def = 0x5dc,
604
+		.link_freq_index = LINK_FREQ_396M_INDEX,
605
+		.reg_list = gc2093_1080p_25fps_hdr_settings,
606
+		.reg_num = ARRAY_SIZE(gc2093_1080p_25fps_hdr_settings),
454607 		.hdr_mode = HDR_X2,
455608 		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
456609 		.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
....@@ -585,6 +738,7 @@
585738 
586739 	switch (ctrl->id) {
587740 	case V4L2_CID_EXPOSURE:
741
+		dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
588742 		if (gc2093->cur_mode->hdr_mode != NO_HDR)
589743 			goto ctrl_end;
590744 		dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
....@@ -594,29 +748,36 @@
594748 					ctrl->val & 0xff);
595749 		break;
596750 	case V4L2_CID_ANALOGUE_GAIN:
751
+		dev_dbg(gc2093->dev, "set gain value 0x%x, mode: %d\n",
752
+				ctrl->val, gc2093->cur_mode->hdr_mode);
597753 		if (gc2093->cur_mode->hdr_mode != NO_HDR)
598754 			goto ctrl_end;
599755 		dev_dbg(gc2093->dev, "set gain value 0x%x\n", ctrl->val);
600756 		gc2093_set_gain(gc2093, ctrl->val);
601757 		break;
602758 	case V4L2_CID_VBLANK:
759
+		dev_dbg(gc2093->dev, "set blank value 0x%x\n", ctrl->val);
603760 		vts = gc2093->cur_mode->height + ctrl->val;
604761 		gc2093->cur_vts = vts;
605762 		ret = gc2093_write_reg(gc2093, GC2093_REG_VTS_H,
606763 				       (vts >> 8) & 0x3f);
607764 		ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L,
608765 					vts & 0xff);
766
+		if (!ret)
767
+			gc2093->cur_vts = ctrl->val + gc2093->cur_mode->height;
609768 		if (gc2093->cur_vts != gc2093->cur_mode->vts_def)
610769 			gc2093_modify_fps_info(gc2093);
611770 		dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val);
612771 		break;
613772 	case V4L2_CID_HFLIP:
614
-			regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
615
-					   MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
773
+		dev_dbg(gc2093->dev, "set hflip 0x%x\n", ctrl->val);
774
+		regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
775
+				   MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
616776 		break;
617777 	case V4L2_CID_VFLIP:
618
-			regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
619
-					   FLIP_MASK,  ctrl->val ? FLIP_MASK : 0);
778
+		dev_dbg(gc2093->dev, "set vflip 0x%x\n", ctrl->val);
779
+		regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
780
+				   FLIP_MASK,  ctrl->val ? FLIP_MASK : 0);
620781 		break;
621782 	default:
622783 		dev_warn(gc2093->dev, "%s Unhandled id:0x%x, val:0x%x\n",
....@@ -673,7 +834,7 @@
673834 					   h_blank, h_blank, 1, h_blank);
674835 	if (gc2093->hblank)
675836 		gc2093->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
676
-
837
+	gc2093->cur_fps = mode->max_fps;
677838 	vblank_def = mode->vts_def - mode->height;
678839 	gc2093->cur_vts = mode->vts_def;
679840 	gc2093->vblank = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
....@@ -820,11 +981,24 @@
820981 	strlcpy(inf->base.module, gc2093->module_name, sizeof(inf->base.module));
821982 }
822983 
984
+static int gc2093_get_channel_info(struct gc2093 *gc2093,
985
+				   struct rkmodule_channel_info *ch_info)
986
+{
987
+	if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
988
+		return -EINVAL;
989
+	ch_info->vc = gc2093->cur_mode->vc[ch_info->index];
990
+	ch_info->width = gc2093->cur_mode->width;
991
+	ch_info->height = gc2093->cur_mode->height;
992
+	ch_info->bus_fmt = GC2093_MEDIA_BUS_FMT;
993
+	return 0;
994
+}
995
+
823996 static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
824997 {
825998 	struct gc2093 *gc2093 = to_gc2093(sd);
826999 	struct preisp_hdrae_exp_s *hdrae_exp = arg;
8271000 	struct rkmodule_hdr_cfg *hdr_cfg;
1001
+	struct rkmodule_channel_info *ch_info;
8281002 	long ret = 0;
8291003 	u32 i, h, w;
8301004 	u32 stream = 0;
....@@ -914,15 +1088,18 @@
9141088 		hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
9151089 		w = gc2093->cur_mode->width;
9161090 		h = gc2093->cur_mode->height;
917
-		for (i = 0; i < gc2093->cfg_num; i++) {
1091
+		for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
9181092 			if (w == supported_modes[i].width &&
9191093 			h == supported_modes[i].height &&
9201094 			supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
9211095 				gc2093->cur_mode = &supported_modes[i];
9221096 				break;
9231097 			}
1098
+			dev_err(gc2093->dev, "i:%d,w:%d, h:%d, hdr:%d\n",
1099
+					i, supported_modes[i].width, supported_modes[i].height,
1100
+					supported_modes[i].hdr_mode);
9241101 		}
925
-		if (i == gc2093->cfg_num) {
1102
+		if (i == ARRAY_SIZE(supported_modes)) {
9261103 			dev_err(gc2093->dev, "not find hdr mode:%d %dx%d config\n",
9271104 				hdr_cfg->hdr_mode, w, h);
9281105 			ret = -EINVAL;
....@@ -958,6 +1135,10 @@
9581135 			usleep_range(delay_us, delay_us + 2000);
9591136 		}
9601137 		break;
1138
+	case RKMODULE_GET_CHANNEL_INFO:
1139
+		ch_info = (struct rkmodule_channel_info *)arg;
1140
+		ret = gc2093_get_channel_info(gc2093, ch_info);
1141
+		break;
9611142 	default:
9621143 		ret = -ENOIOCTLCMD;
9631144 		break;
....@@ -990,8 +1171,16 @@
9901171 			}
9911172 		}
9921173 	}
1174
+	dev_info(gc2093->dev,
1175
+		 "%dx%d@%d, mode %d, vts 0x%x\n",
1176
+		 gc2093->cur_mode->width,
1177
+		 gc2093->cur_mode->height,
1178
+		 gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
1179
+		 gc2093->cur_mode->hdr_mode,
1180
+		 gc2093->cur_vts);
1181
+	dev_info(gc2093->dev, "is_tb:%d\n", gc2093->is_thunderboot);
9931182 	return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
994
-				GC2093_MODE_STREAMING);
1183
+							GC2093_MODE_STREAMING);
9951184 }
9961185 
9971186 static int __gc2093_stop_stream(struct gc2093 *gc2093)
....@@ -1013,6 +1202,7 @@
10131202 	struct rkmodule_inf *inf;
10141203 	struct rkmodule_hdr_cfg *hdr;
10151204 	struct preisp_hdrae_exp_s *hdrae;
1205
+	struct rkmodule_channel_info *ch_info;
10161206 	long ret = 0;
10171207 	u32 stream = 0;
10181208 
....@@ -1082,6 +1272,21 @@
10821272 		else
10831273 			ret = -EFAULT;
10841274 		break;
1275
+	case RKMODULE_GET_CHANNEL_INFO:
1276
+		ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1277
+		if (!ch_info) {
1278
+			ret = -ENOMEM;
1279
+			return ret;
1280
+		}
1281
+
1282
+		ret = gc2093_ioctl(sd, cmd, ch_info);
1283
+		if (!ret) {
1284
+			ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1285
+			if (ret)
1286
+				ret = -EFAULT;
1287
+		}
1288
+		kfree(ch_info);
1289
+		break;
10851290 	default:
10861291 		ret = -ENOIOCTLCMD;
10871292 		break;
....@@ -1100,11 +1305,17 @@
11001305 	fps = DIV_ROUND_CLOSEST(gc2093->cur_mode->max_fps.denominator,
11011306 					gc2093->cur_mode->max_fps.numerator);
11021307 
1103
-	dev_info(gc2093->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1104
-				gc2093->cur_mode->width,
1105
-				gc2093->cur_mode->height,
1106
-				fps);
1308
+	dev_info(gc2093->dev,
1309
+		 "%dx%d@%d, mode %d, vts 0x%x\n",
1310
+		 gc2093->cur_mode->width,
1311
+		 gc2093->cur_mode->height,
1312
+		 gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
1313
+		 gc2093->cur_mode->hdr_mode,
1314
+		 gc2093->cur_vts);
11071315 
1316
+	dev_info(gc2093->dev,
1317
+		 "stream:%d\n, on:%d",
1318
+		 gc2093->streaming, on);
11081319 	mutex_lock(&gc2093->lock);
11091320 	on = !!on;
11101321 	if (on == gc2093->streaming)
....@@ -1151,7 +1362,10 @@
11511362 	struct gc2093 *gc2093 = to_gc2093(sd);
11521363 	const struct gc2093_mode *mode = gc2093->cur_mode;
11531364 
1154
-	fi->interval = mode->max_fps;
1365
+	if (gc2093->streaming)
1366
+		fi->interval = gc2093->cur_fps;
1367
+	else
1368
+		fi->interval = mode->max_fps;
11551369 
11561370 	return 0;
11571371 }
....@@ -1184,9 +1398,7 @@
11841398 				   struct v4l2_subdev_pad_config *cfg,
11851399 				   struct v4l2_subdev_frame_size_enum *fse)
11861400 {
1187
-	struct gc2093 *gc2093 = to_gc2093(sd);
1188
-
1189
-	if (fse->index >= gc2093->cfg_num)
1401
+	if (fse->index >= ARRAY_SIZE(supported_modes))
11901402 		return -EINVAL;
11911403 
11921404 	if (fse->code != GC2093_MEDIA_BUS_FMT)
....@@ -1203,9 +1415,7 @@
12031415 						  struct v4l2_subdev_pad_config *cfg,
12041416 						  struct v4l2_subdev_frame_interval_enum *fie)
12051417 {
1206
-	struct gc2093 *gc2093 = to_gc2093(sd);
1207
-
1208
-	if (fie->index >= gc2093->cfg_num)
1418
+	if (fie->index >= ARRAY_SIZE(supported_modes))
12091419 		return -EINVAL;
12101420 
12111421 	fie->code = GC2093_MEDIA_BUS_FMT;
....@@ -1401,6 +1611,78 @@
14011611 			   gc2093_runtime_resume, NULL)
14021612 };
14031613 
1614
+
1615
+#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
1616
+static void find_terminal_resolution(struct gc2093 *gc2093)
1617
+{
1618
+	int i = 0;
1619
+	const struct gc2093_mode *mode = NULL;
1620
+	const struct gc2093_mode *fit_mode = NULL;
1621
+	u32 cur_fps = 0;
1622
+	u32 dst_fps = 0;
1623
+	u32 tmp_fps = 0;
1624
+	u32 rk_cam_hdr = get_rk_cam_hdr();
1625
+	u32 rk_cam_w = get_rk_cam_w();
1626
+	u32 rk_cam_h = get_rk_cam_h();
1627
+	u32 rk_cam_fps = get_rk_cam_fps();
1628
+
1629
+	if (rk_cam_w == 0 || rk_cam_h == 0 ||
1630
+	    rk_cam_fps == 0)
1631
+		goto err_find_res;
1632
+
1633
+	dev_info(gc2093->dev, "find resolution width: %d, height: %d, hdr: %d, fps: %d\n",
1634
+		 rk_cam_w, rk_cam_h, rk_cam_hdr, rk_cam_fps);
1635
+	dst_fps = rk_cam_fps;
1636
+	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1637
+		mode = &supported_modes[i];
1638
+		cur_fps = mode->max_fps.denominator / mode->max_fps.numerator;
1639
+		if (mode->width == rk_cam_w && mode->height == rk_cam_h &&
1640
+		    mode->hdr_mode == rk_cam_hdr) {
1641
+			if (cur_fps == dst_fps) {
1642
+				gc2093->cur_mode = mode;
1643
+				return;
1644
+			}
1645
+			if (cur_fps >= dst_fps) {
1646
+				if (fit_mode) {
1647
+					tmp_fps = fit_mode->max_fps.denominator /
1648
+							  fit_mode->max_fps.numerator;
1649
+					if (tmp_fps - dst_fps > cur_fps - dst_fps)
1650
+						fit_mode = mode;
1651
+				} else {
1652
+					fit_mode = mode;
1653
+				}
1654
+			}
1655
+		}
1656
+	}
1657
+	if (fit_mode) {
1658
+		gc2093->cur_mode = fit_mode;
1659
+		return;
1660
+	}
1661
+err_find_res:
1662
+	dev_err(gc2093->dev, "not match %dx%d@%dfps mode %d\n!",
1663
+		rk_cam_w, rk_cam_h, dst_fps, rk_cam_hdr);
1664
+	gc2093->cur_mode = &supported_modes[0];
1665
+}
1666
+#else
1667
+static void find_terminal_resolution(struct gc2093 *gc2093)
1668
+{
1669
+	u32 hdr_mode = 0;
1670
+	struct device_node *node = gc2093->dev->of_node;
1671
+	int i = 0;
1672
+
1673
+	of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1674
+	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1675
+		if (hdr_mode == supported_modes[i].hdr_mode) {
1676
+			gc2093->cur_mode = &supported_modes[i];
1677
+			break;
1678
+		}
1679
+	}
1680
+	if (i == ARRAY_SIZE(supported_modes))
1681
+		gc2093->cur_mode = &supported_modes[0];
1682
+
1683
+}
1684
+#endif
1685
+
14041686 static int gc2093_probe(struct i2c_client *client,
14051687 			 const struct i2c_device_id *id)
14061688 {
....@@ -1448,6 +1730,8 @@
14481730 		return -EINVAL;
14491731 	}
14501732 
1733
+	find_terminal_resolution(gc2093);
1734
+
14511735 	gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
14521736 	if (IS_ERR(gc2093->reset_gpio))
14531737 		dev_warn(dev, "Failed to get reset-gpios\n");
....@@ -1463,11 +1747,6 @@
14631747 	}
14641748 
14651749 	mutex_init(&gc2093->lock);
1466
-
1467
-	/* set default mode */
1468
-	gc2093->cur_mode = &supported_modes[0];
1469
-	gc2093->cfg_num = ARRAY_SIZE(supported_modes);
1470
-	gc2093->cur_vts = gc2093->cur_mode->vts_def;
14711750 
14721751 	sd = &gc2093->subdev;
14731752 	v4l2_i2c_subdev_init(sd, client, &gc2093_subdev_ops);