| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores |
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| 3 | 4 | * |
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| 4 | 5 | * Integrated Consumer Infrared Controller |
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| 5 | 6 | * |
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| 6 | 7 | * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net> |
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| 7 | | - * |
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| 8 | | - * This program is free software; you can redistribute it and/or |
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| 9 | | - * modify it under the terms of the GNU General Public License |
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| 10 | | - * as published by the Free Software Foundation; either version 2 |
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| 11 | | - * of the License, or (at your option) any later version. |
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| 12 | | - * |
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| 13 | | - * This program is distributed in the hope that it will be useful, |
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| 14 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 15 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 16 | | - * GNU General Public License for more details. |
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| 17 | 8 | */ |
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| 18 | 9 | |
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| 19 | 10 | #include <linux/slab.h> |
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| .. | .. |
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| 549 | 540 | ror = stats & STATS_ROR; /* Rx FIFO Over Run */ |
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| 550 | 541 | |
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| 551 | 542 | tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ |
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| 552 | | - rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */ |
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| 543 | + rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */ |
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| 553 | 544 | rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ |
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| 554 | 545 | roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ |
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| 555 | 546 | |
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| .. | .. |
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| 638 | 629 | events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; |
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| 639 | 630 | } |
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| 640 | 631 | if (v) { |
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| 641 | | - /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */ |
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| 632 | + /* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */ |
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| 642 | 633 | cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v); |
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| 643 | 634 | cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl); |
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| 644 | 635 | *handled = true; |
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| .. | .. |
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| 697 | 688 | } |
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| 698 | 689 | |
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| 699 | 690 | v = (unsigned) pulse_width_count_to_ns( |
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| 700 | | - (u16) (p->hw_fifo_data & FIFO_RXTX), divider); |
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| 691 | + (u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000; |
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| 701 | 692 | if (v > IR_MAX_DURATION) |
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| 702 | 693 | v = IR_MAX_DURATION; |
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| 703 | 694 | |
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| 704 | | - init_ir_raw_event(&p->ir_core_data); |
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| 705 | | - p->ir_core_data.pulse = u; |
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| 706 | | - p->ir_core_data.duration = v; |
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| 707 | | - p->ir_core_data.timeout = w; |
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| 695 | + p->ir_core_data = (struct ir_raw_event) |
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| 696 | + { .pulse = u, .duration = v, .timeout = w }; |
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| 708 | 697 | |
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| 709 | 698 | v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns %s %s\n", |
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| 710 | 699 | v, u ? "mark" : "space", w ? "(timed out)" : ""); |
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