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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/media/dvb-frontends/drxd_hard.c
....@@ -1,20 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
34  *
45  * Copyright (C) 2003-2007 Micronas
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public License
8
- * version 2 only, as published by the Free Software Foundation.
9
- *
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
15
- *
16
- * To obtain the license, point your browser to
17
- * http://www.gnu.org/copyleft/gpl.html
186  */
197 
208 #include <linux/kernel.h>
....@@ -1144,6 +1132,8 @@
11441132 
11451133 static int InitCC(struct drxd_state *state)
11461134 {
1135
+	int status = 0;
1136
+
11471137 	if (state->osc_clock_freq == 0 ||
11481138 	    state->osc_clock_freq > 20000 ||
11491139 	    (state->osc_clock_freq % 4000) != 0) {
....@@ -1151,14 +1141,17 @@
11511141 		return -1;
11521142 	}
11531143 
1154
-	Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1155
-	Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1156
-		CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1157
-	Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1158
-	Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1159
-	Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1144
+	status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1145
+	status |= Write16(state, CC_REG_PLL_MODE__A,
1146
+				CC_REG_PLL_MODE_BYPASS_PLL |
1147
+				CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1148
+	status |= Write16(state, CC_REG_REF_DIVIDE__A,
1149
+				state->osc_clock_freq / 4000, 0);
1150
+	status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL,
1151
+				0);
1152
+	status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
11601153 
1161
-	return 0;
1154
+	return status;
11621155 }
11631156 
11641157 static int ResetECOD(struct drxd_state *state)
....@@ -1312,7 +1305,10 @@
13121305 	int status = 0, ret;
13131306 	u16 errCode;
13141307 
1315
-	Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1308
+	status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1309
+	if (status < 0)
1310
+		return status;
1311
+
13161312 	SC_WaitForReady(state);
13171313 
13181314 	ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
....@@ -1339,9 +1335,9 @@
13391335 			break;
13401336 		}
13411337 		SC_WaitForReady(state);
1342
-		Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1343
-		Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1344
-		Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1338
+		status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1339
+		status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1340
+		status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
13451341 
13461342 		SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
13471343 	} while (0);
....@@ -1516,14 +1512,14 @@
15161512 			switch (deviceId) {
15171513 			case 4:
15181514 				state->diversity = 1;
1519
-				/* fall through */
1515
+				fallthrough;
15201516 			case 3:
15211517 			case 7:
15221518 				state->PGA = 1;
15231519 				break;
15241520 			case 6:
15251521 				state->diversity = 1;
1526
-				/* fall through */
1522
+				fallthrough;
15271523 			case 5:
15281524 			case 8:
15291525 				break;
....@@ -1970,7 +1966,7 @@
19701966 		switch (p->transmission_mode) {
19711967 		default:	/* Not set, detect it automatically */
19721968 			operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1973
-			/* fall through - try first guess DRX_FFTMODE_8K */
1969
+			fallthrough;	/* try first guess DRX_FFTMODE_8K */
19741970 		case TRANSMISSION_MODE_8K:
19751971 			transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
19761972 			if (state->type_A) {
....@@ -2143,7 +2139,7 @@
21432139 		switch (p->modulation) {
21442140 		default:
21452141 			operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2146
-			/* fall through - try first guess DRX_CONSTELLATION_QAM64 */
2142
+			fallthrough;	/* try first guess DRX_CONSTELLATION_QAM64 */
21472143 		case QAM_64:
21482144 			transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
21492145 			if (state->type_A) {
....@@ -2255,61 +2251,41 @@
22552251 		case DRX_CHANNEL_LOW:
22562252 			transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
22572253 			status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2258
-			if (status < 0)
2259
-				break;
22602254 			break;
22612255 		case DRX_CHANNEL_HIGH:
22622256 			transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
22632257 			status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2264
-			if (status < 0)
2265
-				break;
22662258 			break;
2267
-
22682259 		}
22692260 
22702261 		switch (p->code_rate_HP) {
22712262 		case FEC_1_2:
22722263 			transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2273
-			if (state->type_A) {
2264
+			if (state->type_A)
22742265 				status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2275
-				if (status < 0)
2276
-					break;
2277
-			}
22782266 			break;
22792267 		default:
22802268 			operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2281
-			/* fall through */
2269
+			fallthrough;
22822270 		case FEC_2_3:
22832271 			transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2284
-			if (state->type_A) {
2272
+			if (state->type_A)
22852273 				status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2286
-				if (status < 0)
2287
-					break;
2288
-			}
22892274 			break;
22902275 		case FEC_3_4:
22912276 			transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2292
-			if (state->type_A) {
2277
+			if (state->type_A)
22932278 				status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2294
-				if (status < 0)
2295
-					break;
2296
-			}
22972279 			break;
22982280 		case FEC_5_6:
22992281 			transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2300
-			if (state->type_A) {
2282
+			if (state->type_A)
23012283 				status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2302
-				if (status < 0)
2303
-					break;
2304
-			}
23052284 			break;
23062285 		case FEC_7_8:
23072286 			transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2308
-			if (state->type_A) {
2287
+			if (state->type_A)
23092288 				status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2310
-				if (status < 0)
2311
-					break;
2312
-			}
23132289 			break;
23142290 		}
23152291 		if (status < 0)
....@@ -2325,7 +2301,7 @@
23252301 		switch (p->bandwidth_hz) {
23262302 		case 0:
23272303 			p->bandwidth_hz = 8000000;
2328
-			/* fall through */
2304
+			fallthrough;
23292305 		case 8000000:
23302306 			/* (64/7)*(8/8)*1000000 */
23312307 			bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
....@@ -2972,7 +2948,7 @@
29722948 	kfree(state);
29732949 	return NULL;
29742950 }
2975
-EXPORT_SYMBOL(drxd_attach);
2951
+EXPORT_SYMBOL_GPL(drxd_attach);
29762952 
29772953 MODULE_DESCRIPTION("DRXD driver");
29782954 MODULE_AUTHOR("Micronas");