hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
....@@ -199,13 +199,27 @@
199199
200200 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
201201 {
202
- unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
203202 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
203
+ unsigned int last_s2cr;
204204 u32 reg;
205205 u32 smr;
206206 int i;
207207
208208 /*
209
+ * Some platforms support more than the Arm SMMU architected maximum of
210
+ * 128 stream matching groups. For unknown reasons, the additional
211
+ * groups don't exhibit the same behavior as the architected registers,
212
+ * so limit the groups to 128 until the behavior is fixed for the other
213
+ * groups.
214
+ */
215
+ if (smmu->num_mapping_groups > 128) {
216
+ dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");
217
+ smmu->num_mapping_groups = 128;
218
+ }
219
+
220
+ last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
221
+
222
+ /*
209223 * With some firmware versions writes to S2CR of type FAULT are
210224 * ignored, and writing BYPASS will end up written as FAULT in the
211225 * register. Perform a write to S2CR to detect if this is the case and