update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
..
..
@@ -239,7 +239,7 @@
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 				break;
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 			}
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-			/*Ctrl field, ctrl set type: sig, solic, imm, fence */
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+			/* Ctrl field, ctrl set type: sig, solic, imm, fence */
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 			/* SO wait for conforming application scenarios */
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 			ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
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 				      cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
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@@ -300,7 +300,7 @@
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 				}
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 				ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
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 			} else {
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-				/*sqe num is two */
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+				/* sqe num is two */
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 				for (i = 0; i < wr->num_sge; i++)
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 					set_data_seg(dseg + i, wr->sg_list + i);
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..
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@@ -448,6 +448,82 @@
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 	roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
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 	val = le32_to_cpu(tmp);
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 	roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
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+}
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+
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+static int hns_roce_v1_set_hem(struct hns_roce_dev *hr_dev,
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+			       struct hns_roce_hem_table *table, int obj,
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+			       int step_idx)
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+{
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+	spinlock_t *lock = &hr_dev->bt_cmd_lock;
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+	struct device *dev = hr_dev->dev;
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+	struct hns_roce_hem_iter iter;
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+	void __iomem *bt_cmd;
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+	__le32 bt_cmd_val[2];
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+	__le32 bt_cmd_h = 0;
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+	unsigned long flags;
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+	__le32 bt_cmd_l;
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+	int ret = 0;
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+	u64 bt_ba;
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+	long end;
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+
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+	/* Find the HEM(Hardware Entry Memory) entry */
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+	unsigned long i = (obj & (table->num_obj - 1)) /
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+			  (table->table_chunk_size / table->obj_size);
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+
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+	switch (table->type) {
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+	case HEM_TYPE_QPC:
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+	case HEM_TYPE_MTPT:
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+	case HEM_TYPE_CQC:
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+	case HEM_TYPE_SRQC:
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+		roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
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+			ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
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+		break;
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+	default:
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+		return ret;
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+	}
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+
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+	roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
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+		       ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
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+	roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
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+	roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
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+
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+	/* Currently iter only a chunk */
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+	for (hns_roce_hem_first(table->hem[i], &iter);
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+	     !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
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+		bt_ba = hns_roce_hem_addr(&iter) >> HNS_HW_PAGE_SHIFT;
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+
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+		spin_lock_irqsave(lock, flags);
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+
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+		bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
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+
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+		end = HW_SYNC_TIMEOUT_MSECS;
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+		while (end > 0) {
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+			if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
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+				break;
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+
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+			mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
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+			end -= HW_SYNC_SLEEP_TIME_INTERVAL;
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+		}
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+
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+		if (end <= 0) {
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+			dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
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+			spin_unlock_irqrestore(lock, flags);
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+			return -EBUSY;
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+		}
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+
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+		bt_cmd_l = cpu_to_le32(bt_ba);
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+		roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
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+			       ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
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+			       upper_32_bits(bt_ba));
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+
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+		bt_cmd_val[0] = bt_cmd_l;
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+		bt_cmd_val[1] = bt_cmd_h;
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+		hns_roce_write64_k(bt_cmd_val,
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+				   hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
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+		spin_unlock_irqrestore(lock, flags);
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+	}
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+
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+	return ret;
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 }
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 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
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@@ -1165,7 +1241,7 @@
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 	}
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 	raq->e_raq_buf->map = addr;
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-	/* Configure raq extended address. 48bit 4K align*/
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+	/* Configure raq extended address. 48bit 4K align */
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 	roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
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 	/* Configure raq_shift */
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@@ -2062,11 +2138,6 @@
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 		       CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
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 }
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-static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
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-{
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-	return -EOPNOTSUPP;
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-}
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-
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 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
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 				     enum ib_cq_notify_flags flags)
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 {
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@@ -2765,7 +2836,6 @@
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 		roce_set_field(context->qpc_bytes_16,
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 			       QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
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 			       QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
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-
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 	} else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
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 		roce_set_field(context->qpc_bytes_4,
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 			       QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
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@@ -3798,7 +3868,6 @@
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 	int event_type;
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 	while ((aeqe = next_aeqe_sw_v1(eq))) {
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-
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 		/* Make sure we read the AEQ entry after we have checked the
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 		 * ownership bit
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 		 */
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@@ -3903,7 +3972,6 @@
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 	u32 cqn;
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 	while ((ceqe = next_ceqe_sw_v1(eq))) {
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-
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 		/* Make sure we read CEQ entry after we have checked the
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 		 * ownership bit
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 		 */
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@@ -4347,7 +4415,6 @@
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 static const struct ib_device_ops hns_roce_v1_dev_ops = {
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 	.destroy_qp = hns_roce_v1_destroy_qp,
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-	.modify_cq = hns_roce_v1_modify_cq,
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 	.poll_cq = hns_roce_v1_poll_cq,
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 	.post_recv = hns_roce_v1_post_recv,
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 	.post_send = hns_roce_v1_post_send,
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@@ -4367,7 +4434,7 @@
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 	.set_mtu = hns_roce_v1_set_mtu,
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 	.write_mtpt = hns_roce_v1_write_mtpt,
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 	.write_cqc = hns_roce_v1_write_cqc,
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-	.modify_cq = hns_roce_v1_modify_cq,
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+	.set_hem = hns_roce_v1_set_hem,
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 	.clear_hem = hns_roce_v1_clear_hem,
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 	.modify_qp = hns_roce_v1_modify_qp,
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 	.query_qp = hns_roce_v1_query_qp,