update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/infiniband/hw/bnxt_re/qplib_res.h
..
..
@@ -41,6 +41,29 @@
41
41
 
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 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
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43
 
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+#define CHIP_NUM_57508		0x1750
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+#define CHIP_NUM_57504		0x1751
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+#define CHIP_NUM_57502		0x1752
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+
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+enum bnxt_qplib_wqe_mode {
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+	BNXT_QPLIB_WQE_MODE_STATIC	= 0x00,
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+	BNXT_QPLIB_WQE_MODE_VARIABLE	= 0x01,
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+	BNXT_QPLIB_WQE_MODE_INVALID	= 0x02
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+};
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+
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+struct bnxt_qplib_drv_modes {
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+	u8	wqe_mode;
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+	/* Other modes to follow here */
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+};
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+
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+struct bnxt_qplib_chip_ctx {
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+	u16	chip_num;
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+	u8	chip_rev;
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+	u8	chip_metal;
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+	u16	hw_stats_size;
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+	struct bnxt_qplib_drv_modes modes;
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+};
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+
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 #define PTR_CNT_PER_PG		(PAGE_SIZE / sizeof(void *))
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 #define PTR_MAX_IDX_PER_PG	(PTR_CNT_PER_PG - 1)
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 #define PTR_PG(x)		(((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
..
..
@@ -55,7 +78,8 @@
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 enum bnxt_qplib_hwq_type {
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 	HWQ_TYPE_CTX,
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 	HWQ_TYPE_QUEUE,
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-	HWQ_TYPE_L2_CMPL
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+	HWQ_TYPE_L2_CMPL,
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+	HWQ_TYPE_MR
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 };
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84
 
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 #define MAX_PBL_LVL_0_PGS		1
..
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@@ -63,6 +87,7 @@
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 #define MAX_PBL_LVL_1_PGS_SHIFT		9
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 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2	256
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 #define MAX_PBL_LVL_2_PGS		(256 * 512)
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+#define MAX_PDL_LVL_SHIFT               9
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91
 
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 enum bnxt_qplib_pbl_lvl {
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 	PBL_LVL_0,
..
..
@@ -78,6 +103,22 @@
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 #define ROCE_PG_SIZE_8M		(8 * 1024 * 1024)
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 #define ROCE_PG_SIZE_1G		(1024 * 1024 * 1024)
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105
 
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+enum bnxt_qplib_hwrm_pg_size {
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+	BNXT_QPLIB_HWRM_PG_SIZE_4K	= 0,
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+	BNXT_QPLIB_HWRM_PG_SIZE_8K	= 1,
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+	BNXT_QPLIB_HWRM_PG_SIZE_64K	= 2,
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+	BNXT_QPLIB_HWRM_PG_SIZE_2M	= 3,
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+	BNXT_QPLIB_HWRM_PG_SIZE_8M	= 4,
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+	BNXT_QPLIB_HWRM_PG_SIZE_1G	= 5,
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+};
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+
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+struct bnxt_qplib_reg_desc {
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+	u8		bar_id;
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+	resource_size_t	bar_base;
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+	void __iomem	*bar_reg;
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+	size_t		len;
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+};
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+
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 struct bnxt_qplib_pbl {
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 	u32				pg_count;
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 	u32				pg_size;
..
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@@ -85,23 +126,54 @@
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 	dma_addr_t			*pg_map_arr;
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 };
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128
 
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+struct bnxt_qplib_sg_info {
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+	struct ib_umem			*umem;
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+	u32				npages;
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+	u32				pgshft;
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+	u32				pgsize;
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+	bool				nopte;
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+};
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+
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+struct bnxt_qplib_hwq_attr {
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+	struct bnxt_qplib_res		*res;
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+	struct bnxt_qplib_sg_info	*sginfo;
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+	enum bnxt_qplib_hwq_type	type;
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+	u32				depth;
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+	u32				stride;
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+	u32				aux_stride;
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+	u32				aux_depth;
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+};
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+
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 struct bnxt_qplib_hwq {
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 	struct pci_dev			*pdev;
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 	/* lock to protect qplib_hwq */
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 	spinlock_t			lock;
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-	struct bnxt_qplib_pbl		pbl[PBL_LVL_MAX];
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+	struct bnxt_qplib_pbl		pbl[PBL_LVL_MAX + 1];
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 	enum bnxt_qplib_pbl_lvl		level;		/* 0, 1, or 2 */
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 	/* ptr for easy access to the PBL entries */
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 	void				**pbl_ptr;
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 	/* ptr for easy access to the dma_addr */
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 	dma_addr_t			*pbl_dma_ptr;
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 	u32				max_elements;
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+	u32				depth;
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 	u16				element_size;	/* Size of each entry */
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+	u16				qe_ppg;	/* queue entry per page */
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161
 
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 	u32				prod;		/* raw */
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 	u32				cons;		/* raw */
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 	u8				cp_bit;
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 	u8				is_user;
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+	u64				*pad_pg;
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+	u32				pad_stride;
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+	u32				pad_pgofft;
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+};
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+
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+struct bnxt_qplib_db_info {
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+	void __iomem		*db;
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+	void __iomem		*priv_db;
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+	struct bnxt_qplib_hwq	*hwq;
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+	u32			xid;
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+	u32			max_slot;
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177
 };
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178
 
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 /* Tables */
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@@ -111,7 +183,7 @@
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183
 };
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184
 
113
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 struct bnxt_qplib_sgid_tbl {
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-	struct bnxt_qplib_gid		*tbl;
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+	struct bnxt_qplib_gid_info	*tbl;
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 	u16				*hw_id;
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 	u16				max;
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 	u16				active;
..
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@@ -159,6 +231,15 @@
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 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE	64
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 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE	128
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233
 
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+#define MAX_TQM_ALLOC_REQ               48
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+#define MAX_TQM_ALLOC_BLK_SIZE          8
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+struct bnxt_qplib_tqm_ctx {
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+	struct bnxt_qplib_hwq           pde;
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+	u8                              pde_level; /* Original level */
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+	struct bnxt_qplib_hwq           qtbl[MAX_TQM_ALLOC_REQ];
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+	u8                              qcount[MAX_TQM_ALLOC_REQ];
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+};
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+
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 struct bnxt_qplib_ctx {
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 	u32				qpc_count;
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 	struct bnxt_qplib_hwq		qpc_tbl;
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@@ -169,22 +250,18 @@
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 	u32				cq_count;
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 	struct bnxt_qplib_hwq		cq_tbl;
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 	struct bnxt_qplib_hwq		tim_tbl;
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-#define MAX_TQM_ALLOC_REQ		48
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-#define MAX_TQM_ALLOC_BLK_SIZE		8
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-	u8				tqm_count[MAX_TQM_ALLOC_REQ];
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-	struct bnxt_qplib_hwq		tqm_pde;
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-	u32				tqm_pde_level;
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-	struct bnxt_qplib_hwq		tqm_tbl[MAX_TQM_ALLOC_REQ];
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+	struct bnxt_qplib_tqm_ctx	tqm_ctx;
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 	struct bnxt_qplib_stats		stats;
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 	struct bnxt_qplib_vf_res	vf_res;
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+	u64				hwrm_intf_ver;
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 };
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258
 
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 struct bnxt_qplib_res {
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 	struct pci_dev			*pdev;
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+	struct bnxt_qplib_chip_ctx	*cctx;
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 	struct net_device		*netdev;
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263
 
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 	struct bnxt_qplib_rcfw		*rcfw;
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-
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 	struct bnxt_qplib_pd_tbl	pd_tbl;
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 	struct bnxt_qplib_sgid_tbl	sgid_tbl;
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 	struct bnxt_qplib_pkey_tbl	pkey_tbl;
..
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@@ -192,17 +269,88 @@
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 	bool				prio;
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 };
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271
 
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+static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
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+{
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+	return (cctx->chip_num == CHIP_NUM_57508 ||
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+		cctx->chip_num == CHIP_NUM_57504 ||
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+		cctx->chip_num == CHIP_NUM_57502);
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+}
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+
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+static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
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+{
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+	return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
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+					HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
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+}
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+
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+static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
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+{
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+	return bnxt_qplib_is_chip_gen_p5(cctx) ?
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+	       RING_ALLOC_REQ_RING_TYPE_NQ :
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+	       RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
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+}
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+
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+static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
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+{
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+	u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
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+	struct bnxt_qplib_pbl *pbl;
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+
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+	pbl = &hwq->pbl[PBL_LVL_0];
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+	switch (pbl->pg_size) {
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+	case ROCE_PG_SIZE_4K:
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+		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
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+		break;
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+	case ROCE_PG_SIZE_8K:
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+		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
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+		break;
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+	case ROCE_PG_SIZE_64K:
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+		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
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+		break;
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+	case ROCE_PG_SIZE_2M:
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+		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
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+		break;
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+	case ROCE_PG_SIZE_8M:
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+		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
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+		break;
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+	case ROCE_PG_SIZE_1G:
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+		pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
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+		break;
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+	default:
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+		break;
319
+	}
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+
321
+	return pg_size;
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+}
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+
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+static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
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+				      u32 indx, u64 *pg)
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+{
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+	u32 pg_num, pg_idx;
328
+
329
+	pg_num = (indx / hwq->qe_ppg);
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+	pg_idx = (indx % hwq->qe_ppg);
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+	if (pg)
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+		*pg = (u64)&hwq->pbl_ptr[pg_num];
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+	return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
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+}
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+
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+static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
337
+{
338
+	idx += hwq->prod;
339
+	if (idx >= hwq->depth)
340
+		idx -= hwq->depth;
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+	return bnxt_qplib_get_qe(hwq, idx, NULL);
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+}
343
+
195
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 #define to_bnxt_qplib(ptr, type, member)	\
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 	container_of(ptr, type, member)
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346
 
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 struct bnxt_qplib_pd;
199
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 struct bnxt_qplib_dev_attr;
200
349
 
201
-void bnxt_qplib_free_hwq(struct pci_dev *pdev, struct bnxt_qplib_hwq *hwq);
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-int bnxt_qplib_alloc_init_hwq(struct pci_dev *pdev, struct bnxt_qplib_hwq *hwq,
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-			      struct scatterlist *sl, int nmap, u32 *elements,
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-			      u32 elements_per_page, u32 aux, u32 pg_size,
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-			      enum bnxt_qplib_hwq_type hwq_type);
350
+void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
351
+			 struct bnxt_qplib_hwq *hwq);
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+int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
353
+			      struct bnxt_qplib_hwq_attr *hwq_attr);
206
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 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
207
355
 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
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 			struct bnxt_qplib_pd *pd);
..
..
@@ -221,9 +369,90 @@
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 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
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 			 struct net_device *netdev,
223
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 			 struct bnxt_qplib_dev_attr *dev_attr);
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-void bnxt_qplib_free_ctx(struct pci_dev *pdev,
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+void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
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 			 struct bnxt_qplib_ctx *ctx);
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-int bnxt_qplib_alloc_ctx(struct pci_dev *pdev,
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+int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
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 			 struct bnxt_qplib_ctx *ctx,
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-			 bool virt_fn);
376
+			 bool virt_fn, bool is_p5);
377
+
378
+static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)
379
+{
380
+	hwq->prod = (hwq->prod + cnt) % hwq->depth;
381
+}
382
+
383
+static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq,
384
+					    u32 cnt)
385
+{
386
+	hwq->cons = (hwq->cons + cnt) % hwq->depth;
387
+}
388
+
389
+static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
390
+					bool arm)
391
+{
392
+	u32 key;
393
+
394
+	key = info->hwq->cons & (info->hwq->max_elements - 1);
395
+	key |= (CMPL_DOORBELL_IDX_VALID |
396
+		(CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
397
+	if (!arm)
398
+		key |= CMPL_DOORBELL_MASK;
399
+	writel(key, info->db);
400
+}
401
+
402
+static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
403
+				      u32 type)
404
+{
405
+	u64 key = 0;
406
+
407
+	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
408
+	key <<= 32;
409
+	key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
410
+		DBC_DBC_INDEX_MASK;
411
+	writeq(key, info->db);
412
+}
413
+
414
+static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
415
+					   u32 type)
416
+{
417
+	u64 key = 0;
418
+
419
+	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
420
+	key <<= 32;
421
+	key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK;
422
+	writeq(key, info->db);
423
+}
424
+
425
+static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
426
+				       u32 type)
427
+{
428
+	u64 key = 0;
429
+
430
+	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
431
+	key <<= 32;
432
+	writeq(key, info->priv_db);
433
+}
434
+
435
+static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
436
+					 u32 th)
437
+{
438
+	u64 key = 0;
439
+
440
+	key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
441
+	key <<= 32;
442
+	key |=  th & DBC_DBC_INDEX_MASK;
443
+	writeq(key, info->priv_db);
444
+}
445
+
446
+static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
447
+					 struct bnxt_qplib_chip_ctx *cctx,
448
+					 bool arm)
449
+{
450
+	u32 type;
451
+
452
+	type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
453
+	if (bnxt_qplib_is_chip_gen_p5(cctx))
454
+		bnxt_qplib_ring_db(info, type);
455
+	else
456
+		bnxt_qplib_ring_db32(info, arm);
457
+}
229
458
 #endif /* __BNXT_QPLIB_RES_H__ */