update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/hwtracing/coresight/coresight-etm4x.h
..
..
@@ -8,6 +8,7 @@
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8
 
9
9
 #include <asm/local.h>
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 #include <linux/spinlock.h>
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+#include <linux/types.h>
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 #include "coresight-priv.h"
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13
 
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 /*
..
..
@@ -28,6 +29,7 @@
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 #define TRCAUXCTLR			0x018
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 #define TRCEVENTCTL0R			0x020
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 #define TRCEVENTCTL1R			0x024
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+#define TRCRSR				0x028
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 #define TRCSTALLCTLR			0x02C
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 #define TRCTSCTLR			0x030
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 #define TRCSYNCPR			0x034
..
..
@@ -44,13 +46,14 @@
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 #define TRCVDSACCTLR			0x0A4
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 #define TRCVDARCCTLR			0x0A8
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 /* Derived resources registers */
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-#define TRCSEQEVRn(n)			(0x100 + (n * 4))
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+#define TRCSEQEVRn(n)			(0x100 + (n * 4)) /* n = 0-2 */
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 #define TRCSEQRSTEVR			0x118
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 #define TRCSEQSTR			0x11C
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 #define TRCEXTINSELR			0x120
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-#define TRCCNTRLDVRn(n)			(0x140 + (n * 4))
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-#define TRCCNTCTLRn(n)			(0x150 + (n * 4))
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-#define TRCCNTVRn(n)			(0x160 + (n * 4))
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+#define TRCEXTINSELRn(n)		(0x120 + (n * 4)) /* n = 0-3 */
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+#define TRCCNTRLDVRn(n)			(0x140 + (n * 4)) /* n = 0-3 */
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+#define TRCCNTCTLRn(n)			(0x150 + (n * 4)) /* n = 0-3 */
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+#define TRCCNTVRn(n)			(0x160 + (n * 4)) /* n = 0-3 */
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 /* ID registers */
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 #define TRCIDR8				0x180
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 #define TRCIDR9				0x184
..
..
@@ -59,7 +62,7 @@
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 #define TRCIDR12			0x190
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 #define TRCIDR13			0x194
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 #define TRCIMSPEC0			0x1C0
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-#define TRCIMSPECn(n)			(0x1C0 + (n * 4))
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+#define TRCIMSPECn(n)			(0x1C0 + (n * 4)) /* n = 1-7 */
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 #define TRCIDR0				0x1E0
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 #define TRCIDR1				0x1E4
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 #define TRCIDR2				0x1E8
..
..
@@ -68,9 +71,12 @@
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 #define TRCIDR5				0x1F4
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 #define TRCIDR6				0x1F8
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 #define TRCIDR7				0x1FC
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-/* Resource selection registers */
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+/*
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+ * Resource selection registers, n = 2-31.
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+ * First pair (regs 0, 1) is always present and is reserved.
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+ */
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 #define TRCRSCTLRn(n)			(0x200 + (n * 4))
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-/* Single-shot comparator registers */
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+/* Single-shot comparator registers, n = 0-7 */
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 #define TRCSSCCRn(n)			(0x280 + (n * 4))
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 #define TRCSSCSRn(n)			(0x2A0 + (n * 4))
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 #define TRCSSPCICRn(n)			(0x2C0 + (n * 4))
..
..
@@ -80,11 +86,13 @@
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 #define TRCPDCR				0x310
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 #define TRCPDSR				0x314
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 /* Trace registers (0x318-0xEFC) */
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-/* Comparator registers */
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+/* Address Comparator registers n = 0-15 */
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 #define TRCACVRn(n)			(0x400 + (n * 8))
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 #define TRCACATRn(n)			(0x480 + (n * 8))
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+/* Data Value Comparator Value registers, n = 0-7 */
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 #define TRCDVCVRn(n)			(0x500 + (n * 16))
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 #define TRCDVCMRn(n)			(0x580 + (n * 16))
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+/* ContextID/Virtual ContextID comparators, n = 0-7 */
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 #define TRCCIDCVRn(n)			(0x600 + (n * 8))
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 #define TRCVMIDCVRn(n)			(0x640 + (n * 8))
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 #define TRCCIDCCTLR0			0x680
..
..
@@ -120,6 +128,368 @@
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 #define TRCCIDR2			0xFF8
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 #define TRCCIDR3			0xFFC
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130
 
131
+#define TRCRSR_TA			BIT(12)
132
+
133
+/*
134
+ * System instructions to access ETM registers.
135
+ * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
136
+ */
137
+#define ETM4x_OFFSET_TO_REG(x)		((x) >> 2)
138
+
139
+#define ETM4x_CRn(n)			(((n) >> 7) & 0x7)
140
+#define ETM4x_Op2(n)			(((n) >> 4) & 0x7)
141
+#define ETM4x_CRm(n)			((n) & 0xf)
142
+
143
+#include <asm/sysreg.h>
144
+#define ETM4x_REG_NUM_TO_SYSREG(n)				\
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+	sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n))
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+
147
+#define READ_ETM4x_REG(reg)					\
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+	read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg)))
149
+#define WRITE_ETM4x_REG(val, reg)				\
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+	write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))
151
+
152
+#define read_etm4x_sysreg_const_offset(offset)			\
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+	READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset))
154
+
155
+#define write_etm4x_sysreg_const_offset(val, offset)		\
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+	WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))
157
+
158
+#define CASE_READ(res, x)					\
159
+	case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; }
160
+
161
+#define CASE_WRITE(val, x)					\
162
+	case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }
163
+
164
+#define CASE_NOP(__unused, x)					\
165
+	case (x):	/* fall through */
166
+
167
+#define ETE_ONLY_SYSREG_LIST(op, val)		\
168
+	CASE_##op((val), TRCRSR)		\
169
+	CASE_##op((val), TRCEXTINSELRn(1))	\
170
+	CASE_##op((val), TRCEXTINSELRn(2))	\
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+	CASE_##op((val), TRCEXTINSELRn(3))
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+
173
+/* List of registers accessible via System instructions */
174
+#define ETM4x_ONLY_SYSREG_LIST(op, val)		\
175
+	CASE_##op((val), TRCPROCSELR)		\
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+	CASE_##op((val), TRCVDCTLR)		\
177
+	CASE_##op((val), TRCVDSACCTLR)		\
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+	CASE_##op((val), TRCVDARCCTLR)		\
179
+	CASE_##op((val), TRCOSLAR)
180
+
181
+#define ETM_COMMON_SYSREG_LIST(op, val)		\
182
+	CASE_##op((val), TRCPRGCTLR)		\
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+	CASE_##op((val), TRCSTATR)		\
184
+	CASE_##op((val), TRCCONFIGR)		\
185
+	CASE_##op((val), TRCAUXCTLR)		\
186
+	CASE_##op((val), TRCEVENTCTL0R)		\
187
+	CASE_##op((val), TRCEVENTCTL1R)		\
188
+	CASE_##op((val), TRCSTALLCTLR)		\
189
+	CASE_##op((val), TRCTSCTLR)		\
190
+	CASE_##op((val), TRCSYNCPR)		\
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+	CASE_##op((val), TRCCCCTLR)		\
192
+	CASE_##op((val), TRCBBCTLR)		\
193
+	CASE_##op((val), TRCTRACEIDR)		\
194
+	CASE_##op((val), TRCQCTLR)		\
195
+	CASE_##op((val), TRCVICTLR)		\
196
+	CASE_##op((val), TRCVIIECTLR)		\
197
+	CASE_##op((val), TRCVISSCTLR)		\
198
+	CASE_##op((val), TRCVIPCSSCTLR)		\
199
+	CASE_##op((val), TRCSEQEVRn(0))		\
200
+	CASE_##op((val), TRCSEQEVRn(1))		\
201
+	CASE_##op((val), TRCSEQEVRn(2))		\
202
+	CASE_##op((val), TRCSEQRSTEVR)		\
203
+	CASE_##op((val), TRCSEQSTR)		\
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+	CASE_##op((val), TRCEXTINSELR)		\
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+	CASE_##op((val), TRCCNTRLDVRn(0))	\
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+	CASE_##op((val), TRCCNTRLDVRn(1))	\
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+	CASE_##op((val), TRCCNTRLDVRn(2))	\
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+	CASE_##op((val), TRCCNTRLDVRn(3))	\
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+	CASE_##op((val), TRCCNTCTLRn(0))	\
210
+	CASE_##op((val), TRCCNTCTLRn(1))	\
211
+	CASE_##op((val), TRCCNTCTLRn(2))	\
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+	CASE_##op((val), TRCCNTCTLRn(3))	\
213
+	CASE_##op((val), TRCCNTVRn(0))		\
214
+	CASE_##op((val), TRCCNTVRn(1))		\
215
+	CASE_##op((val), TRCCNTVRn(2))		\
216
+	CASE_##op((val), TRCCNTVRn(3))		\
217
+	CASE_##op((val), TRCIDR8)		\
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+	CASE_##op((val), TRCIDR9)		\
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+	CASE_##op((val), TRCIDR10)		\
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+	CASE_##op((val), TRCIDR11)		\
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+	CASE_##op((val), TRCIDR12)		\
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+	CASE_##op((val), TRCIDR13)		\
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+	CASE_##op((val), TRCIMSPECn(0))		\
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+	CASE_##op((val), TRCIMSPECn(1))		\
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+	CASE_##op((val), TRCIMSPECn(2))		\
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+	CASE_##op((val), TRCIMSPECn(3))		\
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+	CASE_##op((val), TRCIMSPECn(4))		\
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+	CASE_##op((val), TRCIMSPECn(5))		\
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+	CASE_##op((val), TRCIMSPECn(6))		\
230
+	CASE_##op((val), TRCIMSPECn(7))		\
231
+	CASE_##op((val), TRCIDR0)		\
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+	CASE_##op((val), TRCIDR1)		\
233
+	CASE_##op((val), TRCIDR2)		\
234
+	CASE_##op((val), TRCIDR3)		\
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+	CASE_##op((val), TRCIDR4)		\
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+	CASE_##op((val), TRCIDR5)		\
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+	CASE_##op((val), TRCIDR6)		\
238
+	CASE_##op((val), TRCIDR7)		\
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+	CASE_##op((val), TRCRSCTLRn(2))		\
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+	CASE_##op((val), TRCRSCTLRn(3))		\
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+	CASE_##op((val), TRCRSCTLRn(4))		\
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+	CASE_##op((val), TRCRSCTLRn(5))		\
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+	CASE_##op((val), TRCRSCTLRn(6))		\
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+	CASE_##op((val), TRCRSCTLRn(7))		\
245
+	CASE_##op((val), TRCRSCTLRn(8))		\
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+	CASE_##op((val), TRCRSCTLRn(9))		\
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+	CASE_##op((val), TRCRSCTLRn(10))	\
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+	CASE_##op((val), TRCRSCTLRn(11))	\
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+	CASE_##op((val), TRCRSCTLRn(12))	\
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+	CASE_##op((val), TRCRSCTLRn(13))	\
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+	CASE_##op((val), TRCRSCTLRn(14))	\
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+	CASE_##op((val), TRCRSCTLRn(15))	\
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+	CASE_##op((val), TRCRSCTLRn(16))	\
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+	CASE_##op((val), TRCRSCTLRn(17))	\
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+	CASE_##op((val), TRCRSCTLRn(18))	\
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+	CASE_##op((val), TRCRSCTLRn(19))	\
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+	CASE_##op((val), TRCRSCTLRn(20))	\
258
+	CASE_##op((val), TRCRSCTLRn(21))	\
259
+	CASE_##op((val), TRCRSCTLRn(22))	\
260
+	CASE_##op((val), TRCRSCTLRn(23))	\
261
+	CASE_##op((val), TRCRSCTLRn(24))	\
262
+	CASE_##op((val), TRCRSCTLRn(25))	\
263
+	CASE_##op((val), TRCRSCTLRn(26))	\
264
+	CASE_##op((val), TRCRSCTLRn(27))	\
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+	CASE_##op((val), TRCRSCTLRn(28))	\
266
+	CASE_##op((val), TRCRSCTLRn(29))	\
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+	CASE_##op((val), TRCRSCTLRn(30))	\
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+	CASE_##op((val), TRCRSCTLRn(31))	\
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+	CASE_##op((val), TRCSSCCRn(0))		\
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+	CASE_##op((val), TRCSSCCRn(1))		\
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+	CASE_##op((val), TRCSSCCRn(2))		\
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+	CASE_##op((val), TRCSSCCRn(3))		\
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+	CASE_##op((val), TRCSSCCRn(4))		\
274
+	CASE_##op((val), TRCSSCCRn(5))		\
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+	CASE_##op((val), TRCSSCCRn(6))		\
276
+	CASE_##op((val), TRCSSCCRn(7))		\
277
+	CASE_##op((val), TRCSSCSRn(0))		\
278
+	CASE_##op((val), TRCSSCSRn(1))		\
279
+	CASE_##op((val), TRCSSCSRn(2))		\
280
+	CASE_##op((val), TRCSSCSRn(3))		\
281
+	CASE_##op((val), TRCSSCSRn(4))		\
282
+	CASE_##op((val), TRCSSCSRn(5))		\
283
+	CASE_##op((val), TRCSSCSRn(6))		\
284
+	CASE_##op((val), TRCSSCSRn(7))		\
285
+	CASE_##op((val), TRCSSPCICRn(0))	\
286
+	CASE_##op((val), TRCSSPCICRn(1))	\
287
+	CASE_##op((val), TRCSSPCICRn(2))	\
288
+	CASE_##op((val), TRCSSPCICRn(3))	\
289
+	CASE_##op((val), TRCSSPCICRn(4))	\
290
+	CASE_##op((val), TRCSSPCICRn(5))	\
291
+	CASE_##op((val), TRCSSPCICRn(6))	\
292
+	CASE_##op((val), TRCSSPCICRn(7))	\
293
+	CASE_##op((val), TRCOSLSR)		\
294
+	CASE_##op((val), TRCACVRn(0))		\
295
+	CASE_##op((val), TRCACVRn(1))		\
296
+	CASE_##op((val), TRCACVRn(2))		\
297
+	CASE_##op((val), TRCACVRn(3))		\
298
+	CASE_##op((val), TRCACVRn(4))		\
299
+	CASE_##op((val), TRCACVRn(5))		\
300
+	CASE_##op((val), TRCACVRn(6))		\
301
+	CASE_##op((val), TRCACVRn(7))		\
302
+	CASE_##op((val), TRCACVRn(8))		\
303
+	CASE_##op((val), TRCACVRn(9))		\
304
+	CASE_##op((val), TRCACVRn(10))		\
305
+	CASE_##op((val), TRCACVRn(11))		\
306
+	CASE_##op((val), TRCACVRn(12))		\
307
+	CASE_##op((val), TRCACVRn(13))		\
308
+	CASE_##op((val), TRCACVRn(14))		\
309
+	CASE_##op((val), TRCACVRn(15))		\
310
+	CASE_##op((val), TRCACATRn(0))		\
311
+	CASE_##op((val), TRCACATRn(1))		\
312
+	CASE_##op((val), TRCACATRn(2))		\
313
+	CASE_##op((val), TRCACATRn(3))		\
314
+	CASE_##op((val), TRCACATRn(4))		\
315
+	CASE_##op((val), TRCACATRn(5))		\
316
+	CASE_##op((val), TRCACATRn(6))		\
317
+	CASE_##op((val), TRCACATRn(7))		\
318
+	CASE_##op((val), TRCACATRn(8))		\
319
+	CASE_##op((val), TRCACATRn(9))		\
320
+	CASE_##op((val), TRCACATRn(10))		\
321
+	CASE_##op((val), TRCACATRn(11))		\
322
+	CASE_##op((val), TRCACATRn(12))		\
323
+	CASE_##op((val), TRCACATRn(13))		\
324
+	CASE_##op((val), TRCACATRn(14))		\
325
+	CASE_##op((val), TRCACATRn(15))		\
326
+	CASE_##op((val), TRCDVCVRn(0))		\
327
+	CASE_##op((val), TRCDVCVRn(1))		\
328
+	CASE_##op((val), TRCDVCVRn(2))		\
329
+	CASE_##op((val), TRCDVCVRn(3))		\
330
+	CASE_##op((val), TRCDVCVRn(4))		\
331
+	CASE_##op((val), TRCDVCVRn(5))		\
332
+	CASE_##op((val), TRCDVCVRn(6))		\
333
+	CASE_##op((val), TRCDVCVRn(7))		\
334
+	CASE_##op((val), TRCDVCMRn(0))		\
335
+	CASE_##op((val), TRCDVCMRn(1))		\
336
+	CASE_##op((val), TRCDVCMRn(2))		\
337
+	CASE_##op((val), TRCDVCMRn(3))		\
338
+	CASE_##op((val), TRCDVCMRn(4))		\
339
+	CASE_##op((val), TRCDVCMRn(5))		\
340
+	CASE_##op((val), TRCDVCMRn(6))		\
341
+	CASE_##op((val), TRCDVCMRn(7))		\
342
+	CASE_##op((val), TRCCIDCVRn(0))		\
343
+	CASE_##op((val), TRCCIDCVRn(1))		\
344
+	CASE_##op((val), TRCCIDCVRn(2))		\
345
+	CASE_##op((val), TRCCIDCVRn(3))		\
346
+	CASE_##op((val), TRCCIDCVRn(4))		\
347
+	CASE_##op((val), TRCCIDCVRn(5))		\
348
+	CASE_##op((val), TRCCIDCVRn(6))		\
349
+	CASE_##op((val), TRCCIDCVRn(7))		\
350
+	CASE_##op((val), TRCVMIDCVRn(0))	\
351
+	CASE_##op((val), TRCVMIDCVRn(1))	\
352
+	CASE_##op((val), TRCVMIDCVRn(2))	\
353
+	CASE_##op((val), TRCVMIDCVRn(3))	\
354
+	CASE_##op((val), TRCVMIDCVRn(4))	\
355
+	CASE_##op((val), TRCVMIDCVRn(5))	\
356
+	CASE_##op((val), TRCVMIDCVRn(6))	\
357
+	CASE_##op((val), TRCVMIDCVRn(7))	\
358
+	CASE_##op((val), TRCCIDCCTLR0)		\
359
+	CASE_##op((val), TRCCIDCCTLR1)		\
360
+	CASE_##op((val), TRCVMIDCCTLR0)		\
361
+	CASE_##op((val), TRCVMIDCCTLR1)		\
362
+	CASE_##op((val), TRCCLAIMSET)		\
363
+	CASE_##op((val), TRCCLAIMCLR)		\
364
+	CASE_##op((val), TRCAUTHSTATUS)		\
365
+	CASE_##op((val), TRCDEVARCH)		\
366
+	CASE_##op((val), TRCDEVID)
367
+
368
+/* List of registers only accessible via memory-mapped interface */
369
+#define ETM_MMAP_LIST(op, val)			\
370
+	CASE_##op((val), TRCDEVTYPE)		\
371
+	CASE_##op((val), TRCPDCR)		\
372
+	CASE_##op((val), TRCPDSR)		\
373
+	CASE_##op((val), TRCDEVAFF0)		\
374
+	CASE_##op((val), TRCDEVAFF1)		\
375
+	CASE_##op((val), TRCLAR)		\
376
+	CASE_##op((val), TRCLSR)		\
377
+	CASE_##op((val), TRCITCTRL)		\
378
+	CASE_##op((val), TRCPIDR4)		\
379
+	CASE_##op((val), TRCPIDR0)		\
380
+	CASE_##op((val), TRCPIDR1)		\
381
+	CASE_##op((val), TRCPIDR2)		\
382
+	CASE_##op((val), TRCPIDR3)
383
+
384
+#define ETM4x_READ_SYSREG_CASES(res)		\
385
+	ETM_COMMON_SYSREG_LIST(READ, (res))	\
386
+	ETM4x_ONLY_SYSREG_LIST(READ, (res))
387
+
388
+#define ETM4x_WRITE_SYSREG_CASES(val)		\
389
+	ETM_COMMON_SYSREG_LIST(WRITE, (val))	\
390
+	ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
391
+
392
+#define ETM_COMMON_SYSREG_LIST_CASES		\
393
+	ETM_COMMON_SYSREG_LIST(NOP, __unused)
394
+
395
+#define ETM4x_ONLY_SYSREG_LIST_CASES		\
396
+	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
397
+
398
+#define ETM4x_SYSREG_LIST_CASES			\
399
+	ETM_COMMON_SYSREG_LIST_CASES		\
400
+	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
401
+
402
+#define ETM4x_MMAP_LIST_CASES		ETM_MMAP_LIST(NOP, __unused)
403
+
404
+/* ETE only supports system register access */
405
+#define ETE_READ_CASES(res)			\
406
+	ETM_COMMON_SYSREG_LIST(READ, (res))	\
407
+	ETE_ONLY_SYSREG_LIST(READ, (res))
408
+
409
+#define ETE_WRITE_CASES(val)			\
410
+	ETM_COMMON_SYSREG_LIST(WRITE, (val))	\
411
+	ETE_ONLY_SYSREG_LIST(WRITE, (val))
412
+
413
+#define ETE_ONLY_SYSREG_LIST_CASES		\
414
+	ETE_ONLY_SYSREG_LIST(NOP, __unused)
415
+
416
+#define read_etm4x_sysreg_offset(offset, _64bit)				\
417
+	({									\
418
+		u64 __val;							\
419
+										\
420
+		if (__builtin_constant_p((offset)))				\
421
+			__val = read_etm4x_sysreg_const_offset((offset));	\
422
+		else								\
423
+			__val = etm4x_sysreg_read((offset), true, (_64bit));	\
424
+		__val;								\
425
+	 })
426
+
427
+#define write_etm4x_sysreg_offset(val, offset, _64bit)			\
428
+	do {								\
429
+		if (__builtin_constant_p((offset)))			\
430
+			write_etm4x_sysreg_const_offset((val),		\
431
+							(offset));	\
432
+		else							\
433
+			etm4x_sysreg_write((val), (offset), true,	\
434
+					   (_64bit));			\
435
+	} while (0)
436
+
437
+
438
+#define etm4x_relaxed_read32(csa, offset)				\
439
+	((u32)((csa)->io_mem ?						\
440
+		 readl_relaxed((csa)->base + (offset)) :		\
441
+		 read_etm4x_sysreg_offset((offset), false)))
442
+
443
+#define etm4x_relaxed_read64(csa, offset)				\
444
+	((u64)((csa)->io_mem ?						\
445
+		 readq_relaxed((csa)->base + (offset)) :		\
446
+		 read_etm4x_sysreg_offset((offset), true)))
447
+
448
+#define etm4x_read32(csa, offset)					\
449
+	({								\
450
+		u32 __val = etm4x_relaxed_read32((csa), (offset));	\
451
+		__iormb(__val);						\
452
+		__val;							\
453
+	 })
454
+
455
+#define etm4x_read64(csa, offset)					\
456
+	({								\
457
+		u64 __val = etm4x_relaxed_read64((csa), (offset));	\
458
+		__iormb(__val);						\
459
+		__val;							\
460
+	 })
461
+
462
+#define etm4x_relaxed_write32(csa, val, offset)				\
463
+	do {								\
464
+		if ((csa)->io_mem)					\
465
+			writel_relaxed((val), (csa)->base + (offset));	\
466
+		else							\
467
+			write_etm4x_sysreg_offset((val), (offset),	\
468
+						  false);		\
469
+	} while (0)
470
+
471
+#define etm4x_relaxed_write64(csa, val, offset)				\
472
+	do {								\
473
+		if ((csa)->io_mem)					\
474
+			writeq_relaxed((val), (csa)->base + (offset));	\
475
+		else							\
476
+			write_etm4x_sysreg_offset((val), (offset),	\
477
+						  true);		\
478
+	} while (0)
479
+
480
+#define etm4x_write32(csa, val, offset)					\
481
+	do {								\
482
+		__iowmb();						\
483
+		etm4x_relaxed_write32((csa), (val), (offset));		\
484
+	} while (0)
485
+
486
+#define etm4x_write64(csa, val, offset)					\
487
+	do {								\
488
+		__iowmb();						\
489
+		etm4x_relaxed_write64((csa), (val), (offset));		\
490
+	} while (0)
491
+
492
+
123
493
 /* ETMv4 resources */
124
494
 #define ETM_MAX_NR_PE			8
125
495
 #define ETMv4_MAX_CNTR			4
..
..
@@ -133,10 +503,9 @@
133
503
 #define ETMv4_MAX_CTXID_CMP		8
134
504
 #define ETM_MAX_VMID_CMP		8
135
505
 #define ETM_MAX_PE_CMP			8
136
-#define ETM_MAX_RES_SEL			16
506
+#define ETM_MAX_RES_SEL			32
137
507
 #define ETM_MAX_SS_CMP			8
138
508
 
139
-#define ETM_ARCH_V4			0x40
140
509
 #define ETMv4_SYNC_MASK			0x1F
141
510
 #define ETM_CYC_THRESHOLD_MASK		0xFFF
142
511
 #define ETM_CYC_THRESHOLD_DEFAULT       0x100
..
..
@@ -174,23 +543,166 @@
174
543
 					 ETM_MODE_EXCL_KERN | \
175
544
 					 ETM_MODE_EXCL_USER)
176
545
 
546
+/*
547
+ * TRCOSLSR.OSLM advertises the OS Lock model.
548
+ * OSLM[2:0] = TRCOSLSR[4:3,0]
549
+ *
550
+ *	0b000 - Trace OS Lock is not implemented.
551
+ *	0b010 - Trace OS Lock is implemented.
552
+ *	0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
553
+ */
554
+#define ETM_OSLOCK_NI		0b000
555
+#define ETM_OSLOCK_PRESENT	0b010
556
+#define ETM_OSLOCK_PE		0b100
557
+
558
+#define ETM_OSLSR_OSLM(oslsr)	((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
559
+
560
+/*
561
+ * TRCDEVARCH Bit field definitions
562
+ * Bits[31:21]	- ARCHITECT = Always Arm Ltd.
563
+ *                * Bits[31:28] = 0x4
564
+ *                * Bits[27:21] = 0b0111011
565
+ * Bit[20]	- PRESENT,  Indicates the presence of this register.
566
+ *
567
+ * Bit[19:16]	- REVISION, Revision of the architecture.
568
+ *
569
+ * Bit[15:0]	- ARCHID, Identifies this component as an ETM
570
+ *                * Bits[15:12] - architecture version of ETM
571
+ *                *             = 4 for ETMv4
572
+ *                * Bits[11:0] = 0xA13, architecture part number for ETM.
573
+ */
574
+#define ETM_DEVARCH_ARCHITECT_MASK		GENMASK(31, 21)
575
+#define ETM_DEVARCH_ARCHITECT_ARM		((0x4 << 28) | (0b0111011 << 21))
576
+#define ETM_DEVARCH_PRESENT			BIT(20)
577
+#define ETM_DEVARCH_REVISION_SHIFT		16
578
+#define ETM_DEVARCH_REVISION_MASK		GENMASK(19, 16)
579
+#define ETM_DEVARCH_REVISION(x)			\
580
+	(((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT)
581
+#define ETM_DEVARCH_ARCHID_MASK			GENMASK(15, 0)
582
+#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT	12
583
+#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK	GENMASK(15, 12)
584
+#define ETM_DEVARCH_ARCHID_ARCH_VER(x)		\
585
+	(((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)
586
+
587
+#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver)			\
588
+	(((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK)
589
+
590
+#define ETM_DEVARCH_ARCHID_ARCH_PART(x)		((x) & 0xfffUL)
591
+
592
+#define ETM_DEVARCH_MAKE_ARCHID(major)			\
593
+	((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
594
+
595
+#define ETM_DEVARCH_ARCHID_ETMv4x		ETM_DEVARCH_MAKE_ARCHID(0x4)
596
+#define ETM_DEVARCH_ARCHID_ETE			ETM_DEVARCH_MAKE_ARCHID(0x5)
597
+
598
+#define ETM_DEVARCH_ID_MASK						\
599
+	(ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
600
+#define ETM_DEVARCH_ETMv4x_ARCH						\
601
+	(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
602
+#define ETM_DEVARCH_ETE_ARCH						\
603
+	(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
604
+
177
605
 #define TRCSTATR_IDLE_BIT		0
178
606
 #define TRCSTATR_PMSTABLE_BIT		1
179
607
 #define ETM_DEFAULT_ADDR_COMP		0
180
608
 
609
+#define TRCSSCSRn_PC			BIT(3)
610
+
181
611
 /* PowerDown Control Register bits */
182
612
 #define TRCPDCR_PU			BIT(3)
183
613
 
184
-/* secure state access levels */
185
-#define ETM_EXLEVEL_S_APP		BIT(8)
186
-#define ETM_EXLEVEL_S_OS		BIT(9)
187
-#define ETM_EXLEVEL_S_NA		BIT(10)
188
-#define ETM_EXLEVEL_S_HYP		BIT(11)
189
-/* non-secure state access levels */
190
-#define ETM_EXLEVEL_NS_APP		BIT(12)
191
-#define ETM_EXLEVEL_NS_OS		BIT(13)
192
-#define ETM_EXLEVEL_NS_HYP		BIT(14)
193
-#define ETM_EXLEVEL_NS_NA		BIT(15)
614
+#define TRCACATR_EXLEVEL_SHIFT		8
615
+
616
+/*
617
+ * Exception level mask for Secure and Non-Secure ELs.
618
+ * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn).
619
+ * The Secure and Non-Secure ELs are always to gether.
620
+ * Non-secure EL3 is never implemented.
621
+ * We use the following generic mask as they appear in different
622
+ * registers and this can be shifted for the appropriate
623
+ * fields.
624
+ */
625
+#define ETM_EXLEVEL_S_APP		BIT(0)	/* Secure EL0		*/
626
+#define ETM_EXLEVEL_S_OS		BIT(1)	/* Secure EL1		*/
627
+#define ETM_EXLEVEL_S_HYP		BIT(2)	/* Secure EL2		*/
628
+#define ETM_EXLEVEL_S_MON		BIT(3)	/* Secure EL3/Monitor	*/
629
+#define ETM_EXLEVEL_NS_APP		BIT(4)	/* NonSecure EL0	*/
630
+#define ETM_EXLEVEL_NS_OS		BIT(5)	/* NonSecure EL1	*/
631
+#define ETM_EXLEVEL_NS_HYP		BIT(6)	/* NonSecure EL2	*/
632
+
633
+#define ETM_EXLEVEL_MASK		(GENMASK(6, 0))
634
+#define ETM_EXLEVEL_S_MASK		(GENMASK(3, 0))
635
+#define ETM_EXLEVEL_NS_MASK		(GENMASK(6, 4))
636
+
637
+/* access level controls in TRCACATRn */
638
+#define TRCACATR_EXLEVEL_SHIFT		8
639
+
640
+/* access level control in TRCVICTLR */
641
+#define TRCVICTLR_EXLEVEL_SHIFT		16
642
+#define TRCVICTLR_EXLEVEL_S_SHIFT	16
643
+#define TRCVICTLR_EXLEVEL_NS_SHIFT	20
644
+
645
+/* secure / non secure masks - TRCVICTLR, IDR3 */
646
+#define TRCVICTLR_EXLEVEL_MASK		(ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHIFT)
647
+#define TRCVICTLR_EXLEVEL_S_MASK	(ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT)
648
+#define TRCVICTLR_EXLEVEL_NS_MASK	(ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT)
649
+
650
+#define ETM_TRCIDR1_ARCH_MAJOR_SHIFT	8
651
+#define ETM_TRCIDR1_ARCH_MAJOR_MASK	(0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
652
+#define ETM_TRCIDR1_ARCH_MAJOR(x)	\
653
+	(((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
654
+#define ETM_TRCIDR1_ARCH_MINOR_SHIFT	4
655
+#define ETM_TRCIDR1_ARCH_MINOR_MASK	(0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT)
656
+#define ETM_TRCIDR1_ARCH_MINOR(x)	\
657
+	(((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT)
658
+#define ETM_TRCIDR1_ARCH_SHIFT		ETM_TRCIDR1_ARCH_MINOR_SHIFT
659
+#define ETM_TRCIDR1_ARCH_MASK		\
660
+	(ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK)
661
+
662
+#define ETM_TRCIDR1_ARCH_ETMv4		0x4
663
+
664
+/*
665
+ * Driver representation of the ETM architecture.
666
+ * The version of an ETM component can be detected from
667
+ *
668
+ * TRCDEVARCH	- CoreSight architected register
669
+ *                - Bits[15:12] - Major version
670
+ *                - Bits[19:16] - Minor version
671
+ *
672
+ * We must rely only on TRCDEVARCH for the version information. Even though,
673
+ * TRCIDR1 also provides the architecture version, it is a "Trace" register
674
+ * and as such must be accessed only with Trace power domain ON. This may
675
+ * not be available at probe time.
676
+ *
677
+ * Now to make certain decisions easier based on the version
678
+ * we use an internal representation of the version in the
679
+ * driver, as follows :
680
+ *
681
+ * ETM_ARCH_VERSION[7:0], where :
682
+ *      Bits[7:4] - Major version
683
+ *      Bits[3:0] - Minro version
684
+ */
685
+#define ETM_ARCH_VERSION(major, minor)		\
686
+	((((major) & 0xfU) << 4) | (((minor) & 0xfU)))
687
+#define ETM_ARCH_MAJOR_VERSION(arch)	(((arch) >> 4) & 0xfU)
688
+#define ETM_ARCH_MINOR_VERSION(arch)	((arch) & 0xfU)
689
+
690
+#define ETM_ARCH_V4	ETM_ARCH_VERSION(4, 0)
691
+#define ETM_ARCH_ETE	ETM_ARCH_VERSION(5, 0)
692
+
693
+/* Interpretation of resource numbers change at ETM v4.3 architecture */
694
+#define ETM_ARCH_V4_3	ETM_ARCH_VERSION(4, 3)
695
+
696
+static inline u8 etm_devarch_to_arch(u32 devarch)
697
+{
698
+	return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch),
699
+				ETM_DEVARCH_REVISION(devarch));
700
+}
701
+
702
+enum etm_impdef_type {
703
+	ETM4_IMPDEF_HISI_CORE_COMMIT,
704
+	ETM4_IMPDEF_FEATURE_MAX,
705
+};
194
706
 
195
707
 /**
196
708
  * struct etmv4_config - configuration information related to an ETMv4
..
..
@@ -222,6 +734,7 @@
222
734
  * @cntr_val:	Sets or returns the value for a counter.
223
735
  * @res_idx:	Resource index selector.
224
736
  * @res_ctrl:	Controls the selection of the resources in the trace unit.
737
+ * @ss_idx:	Single-shot index selector.
225
738
  * @ss_ctrl:	Controls the corresponding single-shot comparator resource.
226
739
  * @ss_status:	The status of the corresponding single-shot comparator.
227
740
  * @ss_pe_cmp:	Selects the PE comparator inputs for Single-shot control.
..
..
@@ -238,6 +751,7 @@
238
751
  * @vmid_mask0:	VM ID comparator mask for comparator 0-3.
239
752
  * @vmid_mask1:	VM ID comparator mask for comparator 4-7.
240
753
  * @ext_inp:	External input selection.
754
+ * @s_ex_level: Secure ELs where tracing is supported.
241
755
  */
242
756
 struct etmv4_config {
243
757
 	u32				mode;
..
..
@@ -264,6 +778,7 @@
264
778
 	u32				cntr_val[ETMv4_MAX_CNTR];
265
779
 	u8				res_idx;
266
780
 	u32				res_ctrl[ETM_MAX_RES_SEL];
781
+	u8				ss_idx;
267
782
 	u32				ss_ctrl[ETM_MAX_SS_CMP];
268
783
 	u32				ss_status[ETM_MAX_SS_CMP];
269
784
 	u32				ss_pe_cmp[ETM_MAX_SS_CMP];
..
..
@@ -280,6 +795,7 @@
280
795
 	u32				vmid_mask0;
281
796
 	u32				vmid_mask1;
282
797
 	u32				ext_inp;
798
+	u8				s_ex_level;
283
799
 };
284
800
 
285
801
 /**
..
..
@@ -316,7 +832,7 @@
316
832
 	u32	trccntctlr[ETMv4_MAX_CNTR];
317
833
 	u32	trccntvr[ETMv4_MAX_CNTR];
318
834
 
319
-	u32	trcrsctlr[ETM_MAX_RES_SEL * 2];
835
+	u32	trcrsctlr[ETM_MAX_RES_SEL];
320
836
 
321
837
 	u32	trcssccr[ETM_MAX_SS_CMP];
322
838
 	u32	trcsscsr[ETM_MAX_SS_CMP];
..
..
@@ -344,12 +860,11 @@
344
860
 /**
345
861
  * struct etm4_drvdata - specifics associated to an ETM component
346
862
  * @base:       Memory mapped base address for this component.
347
- * @dev:        The device entity associated to this component.
348
863
  * @csdev:      Component vitals needed by the framework.
349
864
  * @spinlock:   Only one at a time pls.
350
865
  * @mode:	This tracer's mode, i.e sysFS, Perf or disabled.
351
866
  * @cpu:        The cpu this component is affined to.
352
- * @arch:       ETM version number.
867
+ * @arch:       ETM architecture version.
353
868
  * @nr_pe:	The number of processing entity available for tracing.
354
869
  * @nr_pe_cmp:	The number of processing entity comparator inputs that are
355
870
  *		available for tracing.
..
..
@@ -396,13 +911,20 @@
396
911
  * @nooverflow:	Indicate if overflow prevention is supported.
397
912
  * @atbtrig:	If the implementation can support ATB triggers
398
913
  * @lpoverride:	If the implementation can support low-power state over.
914
+ * @trfcr:	If the CPU supports FEAT_TRF, value of the TRFCR_ELx that
915
+ *		allows tracing at all ELs. We don't want to compute this
916
+ *		at runtime, due to the additional setting of TRFCR_CX when
917
+ *		in EL2. Otherwise, 0.
399
918
  * @config:	structure holding configuration parameters.
919
+ * @save_trfcr:	Saved TRFCR_EL1 register during a CPU PM event.
400
920
  * @save_state:	State to be preserved across power loss
401
921
  * @state_needs_restore: True when there is context to restore after PM exit
922
+ * @skip_power_up: Indicates if an implementation can skip powering up
923
+ *		   the trace unit.
924
+ * @arch_features: Bitmap of arch features of etmv4 devices.
402
925
  */
403
926
 struct etmv4_drvdata {
404
927
 	void __iomem			*base;
405
-	struct device			*dev;
406
928
 	struct coresight_device		*csdev;
407
929
 	spinlock_t			spinlock;
408
930
 	local_t				mode;
..
..
@@ -429,6 +951,7 @@
429
951
 	u8				s_ex_level;
430
952
 	u8				ns_ex_level;
431
953
 	u8				q_support;
954
+	u8				os_lock_model;
432
955
 	bool				sticky_enable;
433
956
 	bool				boot_enable;
434
957
 	bool				os_unlock;
..
..
@@ -444,9 +967,13 @@
444
967
 	bool				nooverflow;
445
968
 	bool				atbtrig;
446
969
 	bool				lpoverride;
970
+	u64				trfcr;
447
971
 	struct etmv4_config		config;
972
+	u64				save_trfcr;
448
973
 	struct etmv4_save_state		*save_state;
449
974
 	bool				state_needs_restore;
975
+	bool				skip_power_up;
976
+	DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
450
977
 };
451
978
 
452
979
 /* Address comparator access types */
..
..
@@ -467,4 +994,12 @@
467
994
 
468
995
 extern const struct attribute_group *coresight_etmv4_groups[];
469
996
 void etm4_config_trace_mode(struct etmv4_config *config);
997
+
998
+u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
999
+void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
1000
+
1001
+static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
1002
+{
1003
+	return drvdata->arch >= ETM_ARCH_ETE;
1004
+}
470
1005
 #endif