update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
..
..
@@ -24,13 +24,70 @@
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 #include "gf100.h"
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 #include "ctxgf100.h"
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26
 
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+#include <core/firmware.h>
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+#include <subdev/acr.h>
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 #include <subdev/secboot.h>
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+#include <nvfw/flcn.h>
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+
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 #include <nvif/class.h>
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+
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+int
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+gm200_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
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+{
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+	nvkm_warn(&gr->base.engine.subdev, "firmware unavailable\n");
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+	return -ENODEV;
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+}
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41
 
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 /*******************************************************************************
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  * PGRAPH engine/subdev functions
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  ******************************************************************************/
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+
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+static void
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+gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
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+{
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+	struct flcn_bl_dmem_desc_v1 hdr;
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+	nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
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+	hdr.code_dma_base = hdr.code_dma_base + adjust;
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+	hdr.data_dma_base = hdr.data_dma_base + adjust;
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+	nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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+	flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr);
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+}
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+
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+static void
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+gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
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+		       struct nvkm_acr_lsfw *lsfw)
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+{
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+	const u64 base = lsfw->offset.img + lsfw->app_start_offset;
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+	const u64 code = base + lsfw->app_resident_code_offset;
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+	const u64 data = base + lsfw->app_resident_data_offset;
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+	const struct flcn_bl_dmem_desc_v1 hdr = {
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+		.ctx_dma = FALCON_DMAIDX_UCODE,
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+		.code_dma_base = code,
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+		.non_sec_code_off = lsfw->app_resident_code_offset,
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+		.non_sec_code_size = lsfw->app_resident_code_size,
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+		.code_entry_point = lsfw->app_imem_entry,
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+		.data_dma_base = data,
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+		.data_size = lsfw->app_resident_data_size,
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+	};
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+
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+	nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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+}
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+
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+const struct nvkm_acr_lsf_func
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+gm200_gr_gpccs_acr = {
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+	.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
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+	.bld_size = sizeof(struct flcn_bl_dmem_desc_v1),
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+	.bld_write = gm200_gr_acr_bld_write,
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+	.bld_patch = gm200_gr_acr_bld_patch,
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+};
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+
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+const struct nvkm_acr_lsf_func
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+gm200_gr_fecs_acr = {
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+	.bld_size = sizeof(struct flcn_bl_dmem_desc_v1),
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+	.bld_write = gm200_gr_acr_bld_write,
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+	.bld_patch = gm200_gr_acr_bld_patch,
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+};
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 int
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 gm200_gr_rops(struct gf100_gr *gr)
..
..
@@ -124,44 +181,6 @@
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 	}
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 }
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-int
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-gm200_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
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-	      int index, struct nvkm_gr **pgr)
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-{
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-	struct gf100_gr *gr;
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-	int ret;
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-
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-	if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
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-		return -ENOMEM;
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-	*pgr = &gr->base;
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-
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-	ret = gf100_gr_ctor(func, device, index, gr);
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-	if (ret)
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-		return ret;
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-
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-	/* Load firmwares for non-secure falcons */
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-	if (!nvkm_secboot_is_managed(device->secboot,
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-				     NVKM_SECBOOT_FALCON_FECS)) {
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-		if ((ret = gf100_gr_ctor_fw(gr, "gr/fecs_inst", &gr->fuc409c)) ||
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-		    (ret = gf100_gr_ctor_fw(gr, "gr/fecs_data", &gr->fuc409d)))
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-			return ret;
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-	}
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-	if (!nvkm_secboot_is_managed(device->secboot,
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-				     NVKM_SECBOOT_FALCON_GPCCS)) {
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-		if ((ret = gf100_gr_ctor_fw(gr, "gr/gpccs_inst", &gr->fuc41ac)) ||
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-		    (ret = gf100_gr_ctor_fw(gr, "gr/gpccs_data", &gr->fuc41ad)))
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-			return ret;
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-	}
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-
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-	if ((ret = gk20a_gr_av_to_init(gr, "gr/sw_nonctx", &gr->fuc_sw_nonctx)) ||
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-	    (ret = gk20a_gr_aiv_to_init(gr, "gr/sw_ctx", &gr->fuc_sw_ctx)) ||
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-	    (ret = gk20a_gr_av_to_init(gr, "gr/sw_bundle_init", &gr->fuc_bundle)) ||
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-	    (ret = gk20a_gr_av_to_method(gr, "gr/sw_method_init", &gr->fuc_method)))
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-		return ret;
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-
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-	return 0;
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-}
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-
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 static const struct gf100_gr_func
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 gm200_gr = {
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 	.oneinit_tiles = gm200_gr_oneinit_tiles,
..
..
@@ -198,7 +217,78 @@
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 };
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 int
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+gm200_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
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+{
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+	int ret;
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+
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+	ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev,
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+						  &gr->fecs.falcon,
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+						  NVKM_ACR_LSF_FECS,
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+						  "gr/fecs_", ver, fwif->fecs);
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+	if (ret)
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+		return ret;
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+
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+	ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev,
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+						  &gr->gpccs.falcon,
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+						  NVKM_ACR_LSF_GPCCS,
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+						  "gr/gpccs_", ver,
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+						  fwif->gpccs);
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+	if (ret)
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+		return ret;
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+
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+	gr->firmware = true;
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+
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+	return gk20a_gr_load_sw(gr, "gr/", ver);
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+}
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+
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+MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin");
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+MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin");
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+
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+MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin");
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+MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin");
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+
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+MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin");
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+MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin");
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+
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+static const struct gf100_gr_fwif
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+gm200_gr_fwif[] = {
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+	{  0, gm200_gr_load, &gm200_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
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+	{ -1, gm200_gr_nofw },
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+	{}
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+};
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+
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+int
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 gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
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 {
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-	return gm200_gr_new_(&gm200_gr, device, index, pgr);
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+	return gf100_gr_new_(gm200_gr_fwif, device, index, pgr);
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 }