update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/nouveau/nouveau_bo.h
..
..
@@ -1,12 +1,13 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
1
+/* SPDX-License-Identifier: MIT */
2
2
 #ifndef __NOUVEAU_BO_H__
3
3
 #define __NOUVEAU_BO_H__
4
-
4
+#include <drm/ttm/ttm_bo_driver.h>
5
5
 #include <drm/drm_gem.h>
6
6
 
7
7
 struct nouveau_channel;
8
+struct nouveau_cli;
9
+struct nouveau_drm;
8
10
 struct nouveau_fence;
9
-struct nvkm_vma;
10
11
 
11
12
 struct nouveau_bo {
12
13
 	struct ttm_buffer_object bo;
..
..
@@ -17,12 +18,16 @@
17
18
 	bool force_coherent;
18
19
 	struct ttm_bo_kmap_obj kmap;
19
20
 	struct list_head head;
21
+	struct list_head io_reserve_lru;
20
22
 
21
23
 	/* protected by ttm_bo_reserve() */
22
24
 	struct drm_file *reserved_by;
23
25
 	struct list_head entry;
24
26
 	int pbbo_index;
25
27
 	bool validate_mapped;
28
+
29
+	/* GPU address space is independent of CPU word size */
30
+	uint64_t offset;
26
31
 
27
32
 	struct list_head vma_list;
28
33
 
..
..
@@ -34,11 +39,6 @@
34
39
 	unsigned mode;
35
40
 
36
41
 	struct nouveau_drm_tile *tile;
37
-
38
-	/* Only valid if allocated via nouveau_gem_new() and iff you hold a
39
-	 * gem reference to it! For debugging, use gem.filp != NULL to test
40
-	 * whether it is valid. */
41
-	struct drm_gem_object gem;
42
42
 
43
43
 	/* protect by the ttm reservation lock */
44
44
 	int pin_refcnt;
..
..
@@ -61,12 +61,14 @@
61
61
 		return -EINVAL;
62
62
 	prev = *pnvbo;
63
63
 
64
-	*pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
65
-	if (prev) {
66
-		struct ttm_buffer_object *bo = &prev->bo;
67
-
68
-		ttm_bo_unref(&bo);
64
+	if (ref) {
65
+		ttm_bo_get(&ref->bo);
66
+		*pnvbo = nouveau_bo(&ref->bo);
67
+	} else {
68
+		*pnvbo = NULL;
69
69
 	}
70
+	if (prev)
71
+		ttm_bo_put(&prev->bo);
70
72
 
71
73
 	return 0;
72
74
 }
..
..
@@ -74,9 +76,13 @@
74
76
 extern struct ttm_bo_driver nouveau_bo_driver;
75
77
 
76
78
 void nouveau_bo_move_init(struct nouveau_drm *);
77
-int  nouveau_bo_new(struct nouveau_cli *, u64 size, int align, u32 flags,
79
+struct nouveau_bo *nouveau_bo_alloc(struct nouveau_cli *, u64 *size, int *align,
80
+				    u32 domain, u32 tile_mode, u32 tile_flags);
81
+int  nouveau_bo_init(struct nouveau_bo *, u64 size, int align, u32 domain,
82
+		     struct sg_table *sg, struct dma_resv *robj);
83
+int  nouveau_bo_new(struct nouveau_cli *, u64 size, int align, u32 domain,
78
84
 		    u32 tile_mode, u32 tile_flags, struct sg_table *sg,
79
-		    struct reservation_object *robj,
85
+		    struct dma_resv *robj,
80
86
 		    struct nouveau_bo **);
81
87
 int  nouveau_bo_pin(struct nouveau_bo *, u32 flags, bool contig);
82
88
 int  nouveau_bo_unpin(struct nouveau_bo *);
..
..
@@ -91,6 +97,8 @@
91
97
 			 bool no_wait_gpu);
92
98
 void nouveau_bo_sync_for_device(struct nouveau_bo *nvbo);
93
99
 void nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo);
100
+void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo);
101
+void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo);
94
102
 
95
103
 /* TODO: submit equivalent to TTM generic API upstream? */
96
104
 static inline void __iomem *
..
..
@@ -114,13 +122,13 @@
114
122
 }
115
123
 
116
124
 static inline int
117
-nouveau_bo_new_pin_map(struct nouveau_cli *cli, u64 size, int align, u32 flags,
125
+nouveau_bo_new_pin_map(struct nouveau_cli *cli, u64 size, int align, u32 domain,
118
126
 		       struct nouveau_bo **pnvbo)
119
127
 {
120
-	int ret = nouveau_bo_new(cli, size, align, flags,
128
+	int ret = nouveau_bo_new(cli, size, align, domain,
121
129
 				 0, 0, NULL, NULL, pnvbo);
122
130
 	if (ret == 0) {
123
-		ret = nouveau_bo_pin(*pnvbo, flags, true);
131
+		ret = nouveau_bo_pin(*pnvbo, domain, true);
124
132
 		if (ret == 0) {
125
133
 			ret = nouveau_bo_map(*pnvbo);
126
134
 			if (ret == 0)
..
..
@@ -131,4 +139,42 @@
131
139
 	}
132
140
 	return ret;
133
141
 }
142
+
143
+int nv04_bo_move_init(struct nouveau_channel *, u32);
144
+int nv04_bo_move_m2mf(struct nouveau_channel *, struct ttm_buffer_object *,
145
+		      struct ttm_resource *, struct ttm_resource *);
146
+
147
+int nv50_bo_move_init(struct nouveau_channel *, u32);
148
+int nv50_bo_move_m2mf(struct nouveau_channel *, struct ttm_buffer_object *,
149
+		      struct ttm_resource *, struct ttm_resource *);
150
+
151
+int nv84_bo_move_exec(struct nouveau_channel *, struct ttm_buffer_object *,
152
+		      struct ttm_resource *, struct ttm_resource *);
153
+
154
+int nva3_bo_move_copy(struct nouveau_channel *, struct ttm_buffer_object *,
155
+		      struct ttm_resource *, struct ttm_resource *);
156
+
157
+int nvc0_bo_move_init(struct nouveau_channel *, u32);
158
+int nvc0_bo_move_m2mf(struct nouveau_channel *, struct ttm_buffer_object *,
159
+		      struct ttm_resource *, struct ttm_resource *);
160
+
161
+int nvc0_bo_move_copy(struct nouveau_channel *, struct ttm_buffer_object *,
162
+		      struct ttm_resource *, struct ttm_resource *);
163
+
164
+int nve0_bo_move_init(struct nouveau_channel *, u32);
165
+int nve0_bo_move_copy(struct nouveau_channel *, struct ttm_buffer_object *,
166
+		      struct ttm_resource *, struct ttm_resource *);
167
+
168
+#define NVBO_WR32_(b,o,dr,f) nouveau_bo_wr32((b), (o)/4 + (dr), (f))
169
+#define NVBO_RD32_(b,o,dr)   nouveau_bo_rd32((b), (o)/4 + (dr))
170
+#define NVBO_RD32(A...) DRF_RD(NVBO_RD32_,                  ##A)
171
+#define NVBO_RV32(A...) DRF_RV(NVBO_RD32_,                  ##A)
172
+#define NVBO_TV32(A...) DRF_TV(NVBO_RD32_,                  ##A)
173
+#define NVBO_TD32(A...) DRF_TD(NVBO_RD32_,                  ##A)
174
+#define NVBO_WR32(A...) DRF_WR(            NVBO_WR32_,      ##A)
175
+#define NVBO_WV32(A...) DRF_WV(            NVBO_WR32_,      ##A)
176
+#define NVBO_WD32(A...) DRF_WD(            NVBO_WR32_,      ##A)
177
+#define NVBO_MR32(A...) DRF_MR(NVBO_RD32_, NVBO_WR32_, u32, ##A)
178
+#define NVBO_MV32(A...) DRF_MV(NVBO_RD32_, NVBO_WR32_, u32, ##A)
179
+#define NVBO_MD32(A...) DRF_MD(NVBO_RD32_, NVBO_WR32_, u32, ##A)
134
180
 #endif