update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
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@@ -1,13 +1,5 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef _DPU_HW_INTERRUPTS_H
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@@ -19,13 +11,6 @@
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 #include "dpu_hw_catalog.h"
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 #include "dpu_hw_util.h"
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 #include "dpu_hw_mdss.h"
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-
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-#define IRQ_SOURCE_MDP		BIT(0)
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-#define IRQ_SOURCE_DSI0		BIT(4)
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-#define IRQ_SOURCE_DSI1		BIT(5)
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-#define IRQ_SOURCE_HDMI		BIT(8)
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-#define IRQ_SOURCE_EDP		BIT(12)
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-#define IRQ_SOURCE_MHL		BIT(16)
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 /**
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  * dpu_intr_type - HW Interrupt Type
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@@ -96,18 +81,6 @@
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  */
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 struct dpu_hw_intr_ops {
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 	/**
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-	 * set_mask - Programs the given interrupt register with the
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-	 *            given interrupt mask. Register value will get overwritten.
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-	 * @intr:	HW interrupt handle
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-	 * @reg_off:	MDSS HW register offset
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-	 * @irqmask:	IRQ mask value
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-	 */
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-	void (*set_mask)(
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-			struct dpu_hw_intr *intr,
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-			uint32_t reg,
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-			uint32_t irqmask);
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-
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-	/**
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 	 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
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 	 *                 Used for all irq related ops
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 	 * @intr_type:		Interrupt type defined in dpu_intr_type
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@@ -177,16 +150,6 @@
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 			struct dpu_hw_intr *intr);
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 	/**
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-	 * clear_interrupt_status - Clears HW interrupt status based on given
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-	 *                          lookup IRQ index.
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-	 * @intr:	HW interrupt handle
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-	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
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-	 */
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-	void (*clear_interrupt_status)(
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-			struct dpu_hw_intr *intr,
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-			int irq_idx);
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-
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-	/**
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 	 * clear_intr_status_nolock() - clears the HW interrupts without lock
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 	 * @intr:	HW interrupt handle
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 	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
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@@ -206,21 +169,6 @@
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 			struct dpu_hw_intr *intr,
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 			int irq_idx,
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 			bool clear);
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-
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-	/**
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-	 * get_valid_interrupts - Gets a mask of all valid interrupt sources
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-	 *                        within DPU. These are actually status bits
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-	 *                        within interrupt registers that specify the
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-	 *                        source of the interrupt in IRQs. For example,
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-	 *                        valid interrupt sources can be MDP, DSI,
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-	 *                        HDMI etc.
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-	 * @intr:	HW interrupt handle
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-	 * @mask:	Returning the interrupt source MASK
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-	 * @return:	0 for success, otherwise failure
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-	 */
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-	int (*get_valid_interrupts)(
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-			struct dpu_hw_intr *intr,
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-			uint32_t *mask);
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 };
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 /**
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@@ -239,6 +187,7 @@
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 	u32 *save_irq_status;
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 	u32 irq_idx_tbl_size;
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 	spinlock_t irq_lock;
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+	unsigned long irq_mask;
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 };
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 /**