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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
....@@ -1,13 +1,5 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
113  */
124 
135 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
....@@ -216,7 +208,7 @@
216208 	INTERLEAVED_RGB_FMT(XBGR8888,
217209 		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
218210 		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
219
-		true, 4, 0,
211
+		false, 4, 0,
220212 		DPU_FETCH_LINEAR, 1),
221213 
222214 	INTERLEAVED_RGB_FMT(RGBA8888,
....@@ -479,90 +471,6 @@
479471 };
480472 
481473 /*
482
- * A5x tile formats tables:
483
- * These tables hold the A5x tile formats supported.
484
- */
485
-static const struct dpu_format dpu_format_map_tile[] = {
486
-	INTERLEAVED_RGB_FMT_TILED(BGR565,
487
-		0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
488
-		C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
489
-		false, 2, 0,
490
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
491
-
492
-	INTERLEAVED_RGB_FMT_TILED(ARGB8888,
493
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
494
-		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
495
-		true, 4, 0,
496
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
497
-
498
-	INTERLEAVED_RGB_FMT_TILED(ABGR8888,
499
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
500
-		C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
501
-		true, 4, 0,
502
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
503
-
504
-	INTERLEAVED_RGB_FMT_TILED(XBGR8888,
505
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
506
-		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
507
-		false, 4, 0,
508
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
509
-
510
-	INTERLEAVED_RGB_FMT_TILED(RGBA8888,
511
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
512
-		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
513
-		true, 4, 0,
514
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
515
-
516
-	INTERLEAVED_RGB_FMT_TILED(BGRA8888,
517
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
518
-		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
519
-		true, 4, 0,
520
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
521
-
522
-	INTERLEAVED_RGB_FMT_TILED(BGRX8888,
523
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
524
-		C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
525
-		false, 4, 0,
526
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
527
-
528
-	INTERLEAVED_RGB_FMT_TILED(XRGB8888,
529
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
530
-		C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
531
-		false, 4, 0,
532
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
533
-
534
-	INTERLEAVED_RGB_FMT_TILED(RGBX8888,
535
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
536
-		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
537
-		false, 4, 0,
538
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
539
-
540
-	INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
541
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
542
-		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
543
-		true, 4, DPU_FORMAT_FLAG_DX,
544
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
545
-
546
-	INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
547
-		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
548
-		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
549
-		true, 4, DPU_FORMAT_FLAG_DX,
550
-		DPU_FETCH_UBWC, 1, DPU_TILE_HEIGHT_TILED),
551
-
552
-	PSEUDO_YUV_FMT_TILED(NV12,
553
-		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
554
-		C1_B_Cb, C2_R_Cr,
555
-		DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
556
-		DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_NV12),
557
-
558
-	PSEUDO_YUV_FMT_TILED(NV21,
559
-		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
560
-		C2_R_Cr, C1_B_Cb,
561
-		DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
562
-		DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_NV12),
563
-};
564
-
565
-/*
566474  * UBWC formats table:
567475  * This table holds the UBWC formats supported.
568476  * If a compression ratio needs to be used for this or any other format,
....@@ -581,7 +489,23 @@
581489 		true, 4, DPU_FORMAT_FLAG_COMPRESSED,
582490 		DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
583491 
492
+	/* ARGB8888 and ABGR8888 purposely have the same color
493
+	 * ordering.  The hardware only supports ABGR8888 UBWC
494
+	 * natively.
495
+	 */
496
+	INTERLEAVED_RGB_FMT_TILED(ARGB8888,
497
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
498
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
499
+		true, 4, DPU_FORMAT_FLAG_COMPRESSED,
500
+		DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
501
+
584502 	INTERLEAVED_RGB_FMT_TILED(XBGR8888,
503
+		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
504
+		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
505
+		false, 4, DPU_FORMAT_FLAG_COMPRESSED,
506
+		DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
507
+
508
+	INTERLEAVED_RGB_FMT_TILED(XRGB8888,
585509 		COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
586510 		C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
587511 		false, 4, DPU_FORMAT_FLAG_COMPRESSED,
....@@ -604,32 +528,6 @@
604528 		C1_B_Cb, C2_R_Cr,
605529 		DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV |
606530 				DPU_FORMAT_FLAG_COMPRESSED,
607
-		DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
608
-};
609
-
610
-static const struct dpu_format dpu_format_map_p010[] = {
611
-	PSEUDO_YUV_FMT_LOOSE(NV12,
612
-		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
613
-		C1_B_Cb, C2_R_Cr,
614
-		DPU_CHROMA_420, (DPU_FORMAT_FLAG_YUV | DPU_FORMAT_FLAG_DX),
615
-		DPU_FETCH_LINEAR, 2),
616
-};
617
-
618
-static const struct dpu_format dpu_format_map_p010_ubwc[] = {
619
-	PSEUDO_YUV_FMT_LOOSE_TILED(NV12,
620
-		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
621
-		C1_B_Cb, C2_R_Cr,
622
-		DPU_CHROMA_420, (DPU_FORMAT_FLAG_YUV | DPU_FORMAT_FLAG_DX |
623
-				DPU_FORMAT_FLAG_COMPRESSED),
624
-		DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
625
-};
626
-
627
-static const struct dpu_format dpu_format_map_tp10_ubwc[] = {
628
-	PSEUDO_YUV_FMT_TILED(NV12,
629
-		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
630
-		C1_B_Cb, C2_R_Cr,
631
-		DPU_CHROMA_420, (DPU_FORMAT_FLAG_YUV | DPU_FORMAT_FLAG_DX |
632
-				DPU_FORMAT_FLAG_COMPRESSED),
633531 		DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
634532 };
635533 
....@@ -668,7 +566,9 @@
668566 {
669567 	static const struct dpu_media_color_map dpu_media_ubwc_map[] = {
670568 		{DRM_FORMAT_ABGR8888, COLOR_FMT_RGBA8888_UBWC},
569
+		{DRM_FORMAT_ARGB8888, COLOR_FMT_RGBA8888_UBWC},
671570 		{DRM_FORMAT_XBGR8888, COLOR_FMT_RGBA8888_UBWC},
571
+		{DRM_FORMAT_XRGB8888, COLOR_FMT_RGBA8888_UBWC},
672572 		{DRM_FORMAT_ABGR2101010, COLOR_FMT_RGBA1010102_UBWC},
673573 		{DRM_FORMAT_XBGR2101010, COLOR_FMT_RGBA1010102_UBWC},
674574 		{DRM_FORMAT_BGR565, COLOR_FMT_RGB565_UBWC},
....@@ -921,7 +821,7 @@
921821 			+ layout->plane_size[2] + layout->plane_size[3];
922822 
923823 		if (!meta)
924
-			goto done;
824
+			return 0;
925825 
926826 		/* configure Y metadata plane */
927827 		layout->plane_addr[2] = base_addr;
....@@ -952,12 +852,11 @@
952852 		layout->plane_addr[1] = 0;
953853 
954854 		if (!meta)
955
-			goto done;
855
+			return 0;
956856 
957857 		layout->plane_addr[2] = base_addr;
958858 		layout->plane_addr[3] = 0;
959859 	}
960
-done:
961860 	return 0;
962861 }
963862 
....@@ -1041,10 +940,11 @@
1041940 		const struct drm_mode_fb_cmd2 *cmd,
1042941 		struct drm_gem_object **bos)
1043942 {
1044
-	int ret, i, num_base_fmt_planes;
943
+	const struct drm_format_info *info;
1045944 	const struct dpu_format *fmt;
1046945 	struct dpu_hw_fmt_layout layout;
1047946 	uint32_t bos_total_size = 0;
947
+	int ret, i;
1048948 
1049949 	if (!msm_fmt || !cmd || !bos) {
1050950 		DRM_ERROR("invalid arguments\n");
....@@ -1052,14 +952,16 @@
1052952 	}
1053953 
1054954 	fmt = to_dpu_format(msm_fmt);
1055
-	num_base_fmt_planes = drm_format_num_planes(fmt->base.pixel_format);
955
+	info = drm_format_info(fmt->base.pixel_format);
956
+	if (!info)
957
+		return -EINVAL;
1056958 
1057959 	ret = dpu_format_get_plane_sizes(fmt, cmd->width, cmd->height,
1058960 			&layout, cmd->pitches);
1059961 	if (ret)
1060962 		return ret;
1061963 
1062
-	for (i = 0; i < num_base_fmt_planes; i++) {
964
+	for (i = 0; i < info->num_planes; i++) {
1063965 		if (!bos[i]) {
1064966 			DRM_ERROR("invalid handle for plane %d\n", i);
1065967 			return -EINVAL;
....@@ -1137,37 +1039,4 @@
11371039 	if (fmt)
11381040 		return &fmt->base;
11391041 	return NULL;
1140
-}
1141
-
1142
-uint32_t dpu_populate_formats(
1143
-		const struct dpu_format_extended *format_list,
1144
-		uint32_t *pixel_formats,
1145
-		uint64_t *pixel_modifiers,
1146
-		uint32_t pixel_formats_max)
1147
-{
1148
-	uint32_t i, fourcc_format;
1149
-
1150
-	if (!format_list || !pixel_formats)
1151
-		return 0;
1152
-
1153
-	for (i = 0, fourcc_format = 0;
1154
-			format_list->fourcc_format && i < pixel_formats_max;
1155
-			++format_list) {
1156
-		/* verify if listed format is in dpu_format_map? */
1157
-
1158
-		/* optionally return modified formats */
1159
-		if (pixel_modifiers) {
1160
-			/* assume same modifier for all fb planes */
1161
-			pixel_formats[i] = format_list->fourcc_format;
1162
-			pixel_modifiers[i++] = format_list->modifier;
1163
-		} else {
1164
-			/* assume base formats grouped together */
1165
-			if (fourcc_format != format_list->fourcc_format) {
1166
-				fourcc_format = format_list->fourcc_format;
1167
-				pixel_formats[i++] = fourcc_format;
1168
-			}
1169
-		}
1170
-	}
1171
-
1172
-	return i;
11731042 }