.. | .. |
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28 | 28 | ADRENO_FW_MAX, |
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29 | 29 | }; |
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30 | 30 | |
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31 | | -enum adreno_quirks { |
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32 | | - ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, |
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33 | | - ADRENO_QUIRK_FAULT_DETECT_MASK = 2, |
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34 | | - ADRENO_QUIRK_LMLOADKILL_DISABLE = 3, |
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35 | | -}; |
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| 31 | +#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) |
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| 32 | +#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) |
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| 33 | +#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) |
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36 | 34 | |
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37 | 35 | struct adreno_rev { |
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38 | 36 | uint8_t core; |
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.. | .. |
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62 | 60 | const char *name; |
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63 | 61 | const char *fw[ADRENO_FW_MAX]; |
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64 | 62 | uint32_t gmem; |
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65 | | - enum adreno_quirks quirks; |
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| 63 | + u64 quirks; |
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66 | 64 | struct msm_gpu *(*init)(struct drm_device *dev); |
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67 | 65 | const char *zapfw; |
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68 | 66 | u32 inactive_period; |
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