hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/drivers/gpu/drm/msm/adreno/a5xx_preempt.c
....@@ -45,9 +45,9 @@
4545 if (!ring)
4646 return;
4747
48
- spin_lock_irqsave(&ring->lock, flags);
48
+ spin_lock_irqsave(&ring->preempt_lock, flags);
4949 wptr = get_wptr(ring);
50
- spin_unlock_irqrestore(&ring->lock, flags);
50
+ spin_unlock_irqrestore(&ring->preempt_lock, flags);
5151
5252 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr);
5353 }
....@@ -62,9 +62,9 @@
6262 bool empty;
6363 struct msm_ringbuffer *ring = gpu->rb[i];
6464
65
- spin_lock_irqsave(&ring->lock, flags);
66
- empty = (get_wptr(ring) == ring->memptrs->rptr);
67
- spin_unlock_irqrestore(&ring->lock, flags);
65
+ spin_lock_irqsave(&ring->preempt_lock, flags);
66
+ empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring));
67
+ spin_unlock_irqrestore(&ring->preempt_lock, flags);
6868
6969 if (!empty)
7070 return ring;
....@@ -132,9 +132,9 @@
132132 }
133133
134134 /* Make sure the wptr doesn't update while we're in motion */
135
- spin_lock_irqsave(&ring->lock, flags);
135
+ spin_lock_irqsave(&ring->preempt_lock, flags);
136136 a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring);
137
- spin_unlock_irqrestore(&ring->lock, flags);
137
+ spin_unlock_irqrestore(&ring->preempt_lock, flags);
138138
139139 /* Set the address of the incoming preemption record */
140140 gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO,
....@@ -210,6 +210,7 @@
210210 a5xx_gpu->preempt[i]->wptr = 0;
211211 a5xx_gpu->preempt[i]->rptr = 0;
212212 a5xx_gpu->preempt[i]->rbase = gpu->rb[i]->iova;
213
+ a5xx_gpu->preempt[i]->rptr_addr = shadowptr(a5xx_gpu, gpu->rb[i]);
213214 }
214215
215216 /* Write a 0 to signal that we aren't switching pagetables */
....@@ -261,7 +262,6 @@
261262 ptr->data = 0;
262263 ptr->cntl = MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE;
263264
264
- ptr->rptr_addr = shadowptr(a5xx_gpu, ring);
265265 ptr->counter = counters_iova;
266266
267267 return 0;