hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/drivers/gpu/drm/mediatek/mtk_dpi.c
....@@ -367,9 +367,6 @@
367367 if (--dpi->refcount != 0)
368368 return;
369369
370
- if (dpi->pinctrl && dpi->pins_gpio)
371
- pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
372
-
373370 mtk_dpi_disable(dpi);
374371 clk_disable_unprepare(dpi->pixel_clk);
375372 clk_disable_unprepare(dpi->engine_clk);
....@@ -393,9 +390,6 @@
393390 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
394391 goto err_pixel;
395392 }
396
-
397
- if (dpi->pinctrl && dpi->pins_dpi)
398
- pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
399393
400394 return 0;
401395
....@@ -525,12 +519,18 @@
525519 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
526520
527521 mtk_dpi_power_off(dpi);
522
+
523
+ if (dpi->pinctrl && dpi->pins_gpio)
524
+ pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
528525 }
529526
530527 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
531528 {
532529 struct mtk_dpi *dpi = bridge_to_dpi(bridge);
533530
531
+ if (dpi->pinctrl && dpi->pins_dpi)
532
+ pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
533
+
534534 mtk_dpi_power_on(dpi);
535535 mtk_dpi_set_display_mode(dpi, &dpi->mode);
536536 mtk_dpi_enable(dpi);