.. | .. |
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5 | 5 | |
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6 | 6 | #include "i915_drv.h" |
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7 | 7 | #include "intel_dram.h" |
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| 8 | +#include "intel_sideband.h" |
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8 | 9 | |
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9 | 10 | struct dram_dimm_info { |
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10 | 11 | u8 size, width, ranks; |
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.. | .. |
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433 | 434 | return 0; |
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434 | 435 | } |
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435 | 436 | |
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| 437 | +static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv) |
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| 438 | +{ |
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| 439 | + struct dram_info *dram_info = &dev_priv->dram_info; |
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| 440 | + u32 val = 0; |
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| 441 | + int ret; |
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| 442 | + |
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| 443 | + ret = sandybridge_pcode_read(dev_priv, |
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| 444 | + ICL_PCODE_MEM_SUBSYSYSTEM_INFO | |
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| 445 | + ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, |
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| 446 | + &val, NULL); |
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| 447 | + if (ret) |
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| 448 | + return ret; |
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| 449 | + |
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| 450 | + if (IS_GEN(dev_priv, 12)) { |
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| 451 | + switch (val & 0xf) { |
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| 452 | + case 0: |
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| 453 | + dram_info->type = INTEL_DRAM_DDR4; |
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| 454 | + break; |
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| 455 | + case 3: |
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| 456 | + dram_info->type = INTEL_DRAM_LPDDR4; |
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| 457 | + break; |
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| 458 | + case 4: |
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| 459 | + dram_info->type = INTEL_DRAM_DDR3; |
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| 460 | + break; |
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| 461 | + case 5: |
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| 462 | + dram_info->type = INTEL_DRAM_LPDDR3; |
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| 463 | + break; |
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| 464 | + default: |
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| 465 | + MISSING_CASE(val & 0xf); |
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| 466 | + return -1; |
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| 467 | + } |
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| 468 | + } else { |
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| 469 | + switch (val & 0xf) { |
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| 470 | + case 0: |
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| 471 | + dram_info->type = INTEL_DRAM_DDR4; |
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| 472 | + break; |
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| 473 | + case 1: |
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| 474 | + dram_info->type = INTEL_DRAM_DDR3; |
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| 475 | + break; |
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| 476 | + case 2: |
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| 477 | + dram_info->type = INTEL_DRAM_LPDDR3; |
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| 478 | + break; |
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| 479 | + case 3: |
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| 480 | + dram_info->type = INTEL_DRAM_LPDDR4; |
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| 481 | + break; |
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| 482 | + default: |
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| 483 | + MISSING_CASE(val & 0xf); |
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| 484 | + return -1; |
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| 485 | + } |
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| 486 | + } |
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| 487 | + |
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| 488 | + dram_info->num_channels = (val & 0xf0) >> 4; |
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| 489 | + dram_info->num_qgv_points = (val & 0xf00) >> 8; |
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| 490 | + |
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| 491 | + return 0; |
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| 492 | +} |
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| 493 | + |
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| 494 | +static int gen11_get_dram_info(struct drm_i915_private *i915) |
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| 495 | +{ |
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| 496 | + int ret = skl_get_dram_info(i915); |
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| 497 | + |
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| 498 | + if (ret) |
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| 499 | + return ret; |
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| 500 | + |
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| 501 | + return icl_pcode_read_mem_global_info(i915); |
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| 502 | +} |
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| 503 | + |
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| 504 | +static int gen12_get_dram_info(struct drm_i915_private *i915) |
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| 505 | +{ |
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| 506 | + /* Always needed for GEN12+ */ |
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| 507 | + i915->dram_info.is_16gb_dimm = true; |
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| 508 | + |
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| 509 | + return icl_pcode_read_mem_global_info(i915); |
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| 510 | +} |
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| 511 | + |
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436 | 512 | void intel_dram_detect(struct drm_i915_private *i915) |
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437 | 513 | { |
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438 | 514 | struct dram_info *dram_info = &i915->dram_info; |
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.. | .. |
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448 | 524 | if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915)) |
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449 | 525 | return; |
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450 | 526 | |
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451 | | - if (IS_GEN9_LP(i915)) |
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| 527 | + if (INTEL_GEN(i915) >= 12) |
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| 528 | + ret = gen12_get_dram_info(i915); |
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| 529 | + else if (INTEL_GEN(i915) >= 11) |
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| 530 | + ret = gen11_get_dram_info(i915); |
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| 531 | + else if (IS_GEN9_LP(i915)) |
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452 | 532 | ret = bxt_get_dram_info(i915); |
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453 | 533 | else |
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454 | 534 | ret = skl_get_dram_info(i915); |
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