hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/drivers/gpu/drm/i915/intel_dram.c
....@@ -5,6 +5,7 @@
55
66 #include "i915_drv.h"
77 #include "intel_dram.h"
8
+#include "intel_sideband.h"
89
910 struct dram_dimm_info {
1011 u8 size, width, ranks;
....@@ -433,6 +434,81 @@
433434 return 0;
434435 }
435436
437
+static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
438
+{
439
+ struct dram_info *dram_info = &dev_priv->dram_info;
440
+ u32 val = 0;
441
+ int ret;
442
+
443
+ ret = sandybridge_pcode_read(dev_priv,
444
+ ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
445
+ ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
446
+ &val, NULL);
447
+ if (ret)
448
+ return ret;
449
+
450
+ if (IS_GEN(dev_priv, 12)) {
451
+ switch (val & 0xf) {
452
+ case 0:
453
+ dram_info->type = INTEL_DRAM_DDR4;
454
+ break;
455
+ case 3:
456
+ dram_info->type = INTEL_DRAM_LPDDR4;
457
+ break;
458
+ case 4:
459
+ dram_info->type = INTEL_DRAM_DDR3;
460
+ break;
461
+ case 5:
462
+ dram_info->type = INTEL_DRAM_LPDDR3;
463
+ break;
464
+ default:
465
+ MISSING_CASE(val & 0xf);
466
+ return -1;
467
+ }
468
+ } else {
469
+ switch (val & 0xf) {
470
+ case 0:
471
+ dram_info->type = INTEL_DRAM_DDR4;
472
+ break;
473
+ case 1:
474
+ dram_info->type = INTEL_DRAM_DDR3;
475
+ break;
476
+ case 2:
477
+ dram_info->type = INTEL_DRAM_LPDDR3;
478
+ break;
479
+ case 3:
480
+ dram_info->type = INTEL_DRAM_LPDDR4;
481
+ break;
482
+ default:
483
+ MISSING_CASE(val & 0xf);
484
+ return -1;
485
+ }
486
+ }
487
+
488
+ dram_info->num_channels = (val & 0xf0) >> 4;
489
+ dram_info->num_qgv_points = (val & 0xf00) >> 8;
490
+
491
+ return 0;
492
+}
493
+
494
+static int gen11_get_dram_info(struct drm_i915_private *i915)
495
+{
496
+ int ret = skl_get_dram_info(i915);
497
+
498
+ if (ret)
499
+ return ret;
500
+
501
+ return icl_pcode_read_mem_global_info(i915);
502
+}
503
+
504
+static int gen12_get_dram_info(struct drm_i915_private *i915)
505
+{
506
+ /* Always needed for GEN12+ */
507
+ i915->dram_info.is_16gb_dimm = true;
508
+
509
+ return icl_pcode_read_mem_global_info(i915);
510
+}
511
+
436512 void intel_dram_detect(struct drm_i915_private *i915)
437513 {
438514 struct dram_info *dram_info = &i915->dram_info;
....@@ -448,7 +524,11 @@
448524 if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
449525 return;
450526
451
- if (IS_GEN9_LP(i915))
527
+ if (INTEL_GEN(i915) >= 12)
528
+ ret = gen12_get_dram_info(i915);
529
+ else if (INTEL_GEN(i915) >= 11)
530
+ ret = gen11_get_dram_info(i915);
531
+ else if (IS_GEN9_LP(i915))
452532 ret = bxt_get_dram_info(i915);
453533 else
454534 ret = skl_get_dram_info(i915);