update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/i915/gvt/reg.h
..
..
@@ -60,8 +60,44 @@
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 #define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
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 #define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
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62
 
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+#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
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+
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+#define PLANE_CTL_ASYNC_FLIP		(1 << 9)
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+#define REG50080_FLIP_TYPE_MASK	0x3
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+#define REG50080_FLIP_TYPE_ASYNC	0x1
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+
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+#define REG_50080(_pipe, _plane) ({ \
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+	typeof(_pipe) (p) = (_pipe); \
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+	typeof(_plane) (q) = (_plane); \
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+	(((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
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+		(_MMIO(0x50090))) : \
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+	(((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
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+		(_MMIO(0x50098))) : \
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+	(((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
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+		(_MMIO(0x5009C))) : \
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+		(_MMIO(0x50080))))); })
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+
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+#define REG_50080_TO_PIPE(_reg) ({ \
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+	typeof(_reg) (reg) = (_reg); \
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+	(((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
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+	(((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
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+	(((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
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+	(INVALID_PIPE)))); })
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+
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+#define REG_50080_TO_PLANE(_reg) ({ \
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+	typeof(_reg) (reg) = (_reg); \
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+	(((reg) == 0x50080 || (reg) == 0x50088 || (reg) == 0x5008C) ? \
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+		(PLANE_PRIMARY) : \
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+	(((reg) == 0x50090 || (reg) == 0x50098 || (reg) == 0x5009C) ? \
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+		(PLANE_SPRITE0) : (I915_MAX_PLANES))); })
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+
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 #define GFX_MODE_BIT_SET_IN_MASK(val, bit) \
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 		((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
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+
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+#define IS_MASKED_BITS_ENABLED(_val, _b) \
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+		(((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
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+#define IS_MASKED_BITS_DISABLED(_val, _b) \
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+		((_val) & _MASKED_BIT_DISABLE(_b))
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 #define FORCEWAKE_RENDER_GEN9_REG 0xa278
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 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
..
..
@@ -71,10 +107,30 @@
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 #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
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 #define FORCEWAKE_ACK_HSW_REG 0x130044
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+#define RB_HEAD_WRAP_CNT_MAX	((1 << 11) - 1)
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+#define RB_HEAD_WRAP_CNT_OFF	21
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 #define RB_HEAD_OFF_MASK	((1U << 21) - (1U << 2))
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 #define RB_TAIL_OFF_MASK	((1U << 21) - (1U << 3))
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 #define RB_TAIL_SIZE_MASK	((1U << 21) - (1U << 12))
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 #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
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 		I915_GTT_PAGE_SIZE)
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+#define PCH_GPIO_BASE	_MMIO(0xc5010)
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+
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+#define PCH_GMBUS0	_MMIO(0xc5100)
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+#define PCH_GMBUS1	_MMIO(0xc5104)
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+#define PCH_GMBUS2	_MMIO(0xc5108)
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+#define PCH_GMBUS3	_MMIO(0xc510c)
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+#define PCH_GMBUS4	_MMIO(0xc5110)
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+#define PCH_GMBUS5	_MMIO(0xc5120)
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+
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+#define TRVATTL3PTRDW(i)	_MMIO(0x4de0 + (i) * 4)
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+#define TRNULLDETCT		_MMIO(0x4de8)
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+#define TRINVTILEDETCT		_MMIO(0x4dec)
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+#define TRVADR			_MMIO(0x4df0)
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+#define TRTTE			_MMIO(0x4df4)
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+#define RING_EXCC(base)		_MMIO((base) + 0x28)
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+#define RING_GFX_MODE(base)	_MMIO((base) + 0x29c)
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+#define VF_GUARDBAND		_MMIO(0x83a4)
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+
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 #endif