update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/i915/gvt/handlers.c
..
..
@@ -3135,9 +3135,10 @@
3135
3135
 	MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3136
3136
 	MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3137
3137
 	MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3138
-	MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS,
3139
-		NULL, gen9_trtte_write);
3140
-	MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
3138
+	MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
3139
+		 NULL, gen9_trtte_write);
3140
+	MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
3141
+		 NULL, gen9_trtt_chicken_write);
3141
3142
 
3142
3143
 	MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
3143
3144
 
..
..
@@ -3686,3 +3687,40 @@
3686
3687
 		intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3687
3688
 		intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3688
3689
 }
3690
+
3691
+void intel_gvt_restore_fence(struct intel_gvt *gvt)
3692
+{
3693
+	struct intel_vgpu *vgpu;
3694
+	int i, id;
3695
+
3696
+	idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3697
+		mmio_hw_access_pre(gvt->gt);
3698
+		for (i = 0; i < vgpu_fence_sz(vgpu); i++)
3699
+			intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i)));
3700
+		mmio_hw_access_post(gvt->gt);
3701
+	}
3702
+}
3703
+
3704
+static inline int mmio_pm_restore_handler(struct intel_gvt *gvt,
3705
+					  u32 offset, void *data)
3706
+{
3707
+	struct intel_vgpu *vgpu = data;
3708
+	struct drm_i915_private *dev_priv = gvt->gt->i915;
3709
+
3710
+	if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE)
3711
+		I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
3712
+
3713
+	return 0;
3714
+}
3715
+
3716
+void intel_gvt_restore_mmio(struct intel_gvt *gvt)
3717
+{
3718
+	struct intel_vgpu *vgpu;
3719
+	int id;
3720
+
3721
+	idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3722
+		mmio_hw_access_pre(gvt->gt);
3723
+		intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu);
3724
+		mmio_hw_access_post(gvt->gt);
3725
+	}
3726
+}