update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/i915/gvt/aperture_gm.c
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@@ -35,12 +35,13 @@
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  */
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 #include "i915_drv.h"
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+#include "gt/intel_ggtt_fencing.h"
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 #include "gvt.h"
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 static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
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 {
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 	struct intel_gvt *gvt = vgpu->gvt;
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-	struct drm_i915_private *dev_priv = gvt->dev_priv;
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+	struct intel_gt *gt = gvt->gt;
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 	unsigned int flags;
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 	u64 start, end, size;
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 	struct drm_mm_node *node;
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@@ -60,12 +61,14 @@
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 		flags = PIN_MAPPABLE;
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 	}
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-	mutex_lock(&dev_priv->drm.struct_mutex);
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-	ret = i915_gem_gtt_insert(&dev_priv->ggtt.vm, node,
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+	mutex_lock(&gt->ggtt->vm.mutex);
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+	mmio_hw_access_pre(gt);
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+	ret = i915_gem_gtt_insert(&gt->ggtt->vm, node,
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 				  size, I915_GTT_PAGE_SIZE,
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 				  I915_COLOR_UNEVICTABLE,
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 				  start, end, flags);
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-	mutex_unlock(&dev_priv->drm.struct_mutex);
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+	mmio_hw_access_post(gt);
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+	mutex_unlock(&gt->ggtt->vm.mutex);
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 	if (ret)
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 		gvt_err("fail to alloc %s gm space from host\n",
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 			high_gm ? "high" : "low");
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@@ -76,7 +79,7 @@
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 static int alloc_vgpu_gm(struct intel_vgpu *vgpu)
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 {
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 	struct intel_gvt *gvt = vgpu->gvt;
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-	struct drm_i915_private *dev_priv = gvt->dev_priv;
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+	struct intel_gt *gt = gvt->gt;
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 	int ret;
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 	ret = alloc_gm(vgpu, false);
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@@ -95,20 +98,21 @@
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 	return 0;
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 out_free_aperture:
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-	mutex_lock(&dev_priv->drm.struct_mutex);
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+	mutex_lock(&gt->ggtt->vm.mutex);
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 	drm_mm_remove_node(&vgpu->gm.low_gm_node);
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-	mutex_unlock(&dev_priv->drm.struct_mutex);
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+	mutex_unlock(&gt->ggtt->vm.mutex);
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 	return ret;
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 }
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 static void free_vgpu_gm(struct intel_vgpu *vgpu)
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 {
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-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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+	struct intel_gvt *gvt = vgpu->gvt;
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+	struct intel_gt *gt = gvt->gt;
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-	mutex_lock(&dev_priv->drm.struct_mutex);
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+	mutex_lock(&gt->ggtt->vm.mutex);
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 	drm_mm_remove_node(&vgpu->gm.low_gm_node);
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 	drm_mm_remove_node(&vgpu->gm.high_gm_node);
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-	mutex_unlock(&dev_priv->drm.struct_mutex);
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+	mutex_unlock(&gt->ggtt->vm.mutex);
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 }
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 /**
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@@ -125,28 +129,29 @@
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 		u32 fence, u64 value)
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 {
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 	struct intel_gvt *gvt = vgpu->gvt;
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-	struct drm_i915_private *dev_priv = gvt->dev_priv;
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-	struct drm_i915_fence_reg *reg;
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+	struct drm_i915_private *i915 = gvt->gt->i915;
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+	struct intel_uncore *uncore = gvt->gt->uncore;
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+	struct i915_fence_reg *reg;
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 	i915_reg_t fence_reg_lo, fence_reg_hi;
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-	assert_rpm_wakelock_held(dev_priv);
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+	assert_rpm_wakelock_held(uncore->rpm);
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-	if (WARN_ON(fence >= vgpu_fence_sz(vgpu)))
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+	if (drm_WARN_ON(&i915->drm, fence >= vgpu_fence_sz(vgpu)))
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 		return;
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 	reg = vgpu->fence.regs[fence];
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-	if (WARN_ON(!reg))
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+	if (drm_WARN_ON(&i915->drm, !reg))
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 		return;
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 	fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
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 	fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
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-	I915_WRITE(fence_reg_lo, 0);
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-	POSTING_READ(fence_reg_lo);
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+	intel_uncore_write(uncore, fence_reg_lo, 0);
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+	intel_uncore_posting_read(uncore, fence_reg_lo);
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-	I915_WRITE(fence_reg_hi, upper_32_bits(value));
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-	I915_WRITE(fence_reg_lo, lower_32_bits(value));
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-	POSTING_READ(fence_reg_lo);
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+	intel_uncore_write(uncore, fence_reg_hi, upper_32_bits(value));
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+	intel_uncore_write(uncore, fence_reg_lo, lower_32_bits(value));
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+	intel_uncore_posting_read(uncore, fence_reg_lo);
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 }
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 static void _clear_vgpu_fence(struct intel_vgpu *vgpu)
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@@ -160,41 +165,43 @@
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 static void free_vgpu_fence(struct intel_vgpu *vgpu)
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 {
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 	struct intel_gvt *gvt = vgpu->gvt;
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-	struct drm_i915_private *dev_priv = gvt->dev_priv;
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-	struct drm_i915_fence_reg *reg;
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+	struct intel_uncore *uncore = gvt->gt->uncore;
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+	struct i915_fence_reg *reg;
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+	intel_wakeref_t wakeref;
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 	u32 i;
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-	if (WARN_ON(!vgpu_fence_sz(vgpu)))
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+	if (drm_WARN_ON(&gvt->gt->i915->drm, !vgpu_fence_sz(vgpu)))
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 		return;
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-	intel_runtime_pm_get(dev_priv);
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+	wakeref = intel_runtime_pm_get(uncore->rpm);
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-	mutex_lock(&dev_priv->drm.struct_mutex);
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+	mutex_lock(&gvt->gt->ggtt->vm.mutex);
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 	_clear_vgpu_fence(vgpu);
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 	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
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 		reg = vgpu->fence.regs[i];
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 		i915_unreserve_fence(reg);
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 		vgpu->fence.regs[i] = NULL;
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 	}
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-	mutex_unlock(&dev_priv->drm.struct_mutex);
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+	mutex_unlock(&gvt->gt->ggtt->vm.mutex);
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-	intel_runtime_pm_put(dev_priv);
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+	intel_runtime_pm_put(uncore->rpm, wakeref);
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 }
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 static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
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 {
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 	struct intel_gvt *gvt = vgpu->gvt;
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-	struct drm_i915_private *dev_priv = gvt->dev_priv;
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-	struct drm_i915_fence_reg *reg;
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+	struct intel_uncore *uncore = gvt->gt->uncore;
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+	struct i915_fence_reg *reg;
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+	intel_wakeref_t wakeref;
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 	int i;
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-	intel_runtime_pm_get(dev_priv);
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+	wakeref = intel_runtime_pm_get(uncore->rpm);
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 	/* Request fences from host */
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-	mutex_lock(&dev_priv->drm.struct_mutex);
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+	mutex_lock(&gvt->gt->ggtt->vm.mutex);
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 	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
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-		reg = i915_reserve_fence(dev_priv);
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+		reg = i915_reserve_fence(gvt->gt->ggtt);
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 		if (IS_ERR(reg))
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 			goto out_free_fence;
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..
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@@ -203,9 +210,10 @@
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 	_clear_vgpu_fence(vgpu);
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-	mutex_unlock(&dev_priv->drm.struct_mutex);
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-	intel_runtime_pm_put(dev_priv);
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+	mutex_unlock(&gvt->gt->ggtt->vm.mutex);
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+	intel_runtime_pm_put(uncore->rpm, wakeref);
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 	return 0;
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+
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 out_free_fence:
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 	gvt_vgpu_err("Failed to alloc fences\n");
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 	/* Return fences to host, if fail */
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@@ -216,8 +224,8 @@
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 		i915_unreserve_fence(reg);
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 		vgpu->fence.regs[i] = NULL;
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 	}
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-	mutex_unlock(&dev_priv->drm.struct_mutex);
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-	intel_runtime_pm_put(dev_priv);
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+	mutex_unlock(&gvt->gt->ggtt->vm.mutex);
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+	intel_runtime_pm_put_unchecked(uncore->rpm);
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 	return -ENOSPC;
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 }
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@@ -311,11 +319,11 @@
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  */
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 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu)
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 {
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-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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+	struct intel_gvt *gvt = vgpu->gvt;
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+	intel_wakeref_t wakeref;
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-	intel_runtime_pm_get(dev_priv);
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-	_clear_vgpu_fence(vgpu);
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-	intel_runtime_pm_put(dev_priv);
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+	with_intel_runtime_pm(gvt->gt->uncore->rpm, wakeref)
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+		_clear_vgpu_fence(vgpu);
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 }
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 /**