update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/i915/display/intel_bw.c
..
..
@@ -20,75 +20,8 @@
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 struct intel_qgv_info {
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 	struct intel_qgv_point points[I915_NUM_QGV_POINTS];
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 	u8 num_points;
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-	u8 num_channels;
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 	u8 t_bl;
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-	enum intel_dram_type dram_type;
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 };
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-
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-static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
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-					  struct intel_qgv_info *qi)
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-{
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-	u32 val = 0;
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-	int ret;
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-
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-	ret = sandybridge_pcode_read(dev_priv,
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-				     ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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-				     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
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-				     &val, NULL);
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-	if (ret)
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-		return ret;
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-
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-	if (IS_GEN(dev_priv, 12)) {
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-		switch (val & 0xf) {
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-		case 0:
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-			qi->dram_type = INTEL_DRAM_DDR4;
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-			break;
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-		case 3:
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-			qi->dram_type = INTEL_DRAM_LPDDR4;
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-			break;
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-		case 4:
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-			qi->dram_type = INTEL_DRAM_DDR3;
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-			break;
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-		case 5:
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-			qi->dram_type = INTEL_DRAM_LPDDR3;
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-			break;
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-		default:
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-			MISSING_CASE(val & 0xf);
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-			break;
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-		}
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-	} else if (IS_GEN(dev_priv, 11)) {
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-		switch (val & 0xf) {
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-		case 0:
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-			qi->dram_type = INTEL_DRAM_DDR4;
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-			break;
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-		case 1:
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-			qi->dram_type = INTEL_DRAM_DDR3;
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-			break;
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-		case 2:
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-			qi->dram_type = INTEL_DRAM_LPDDR3;
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-			break;
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-		case 3:
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-			qi->dram_type = INTEL_DRAM_LPDDR4;
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-			break;
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-		default:
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-			MISSING_CASE(val & 0xf);
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-			break;
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-		}
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-	} else {
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-		MISSING_CASE(INTEL_GEN(dev_priv));
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-		qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
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-	}
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-
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-	qi->num_channels = (val & 0xf0) >> 4;
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-	qi->num_points = (val & 0xf00) >> 8;
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-
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-	if (IS_GEN(dev_priv, 12))
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-		qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
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-	else if (IS_GEN(dev_priv, 11))
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-		qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
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-
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-	return 0;
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-}
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 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
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 					 struct intel_qgv_point *sp,
..
..
@@ -139,11 +72,15 @@
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 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
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 			      struct intel_qgv_info *qi)
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 {
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+	const struct dram_info *dram_info = &dev_priv->dram_info;
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 	int i, ret;
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-	ret = icl_pcode_read_mem_global_info(dev_priv, qi);
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-	if (ret)
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-		return ret;
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+	qi->num_points = dram_info->num_qgv_points;
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+
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+	if (IS_GEN(dev_priv, 12))
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+		qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
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+	else if (IS_GEN(dev_priv, 11))
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+		qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
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 	if (drm_WARN_ON(&dev_priv->drm,
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 			qi->num_points > ARRAY_SIZE(qi->points)))
..
..
@@ -209,7 +146,7 @@
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 {
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 	struct intel_qgv_info qi = {};
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 	bool is_y_tile = true; /* assume y tile may be used */
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-	int num_channels;
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+	int num_channels = dev_priv->dram_info.num_channels;
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 	int deinterleave;
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 	int ipqdepth, ipqdepthpch;
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 	int dclk_max;
..
..
@@ -222,7 +159,6 @@
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 			    "Failed to get memory subsystem information, ignoring bandwidth limits");
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 		return ret;
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 	}
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-	num_channels = qi.num_channels;
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 	deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
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 	dclk_max = icl_sagv_max_dclk(&qi);