update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/bridge/tc358768.c
..
..
@@ -9,6 +9,8 @@
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 #include <linux/gpio/consumer.h>
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 #include <linux/i2c.h>
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 #include <linux/kernel.h>
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+#include <linux/media-bus-format.h>
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+#include <linux/minmax.h>
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 #include <linux/module.h>
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 #include <linux/regmap.h>
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 #include <linux/regulator/consumer.h>
..
..
@@ -147,6 +149,7 @@
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149
 
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 	u32 pd_lines; /* number of Parallel Port Input Data Lines */
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 	u32 dsi_lanes; /* number of DSI Lanes */
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+	u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
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153
 
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 	/* Parameters for PLL programming */
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 	u32 fbd;	/* PLL feedback divider */
..
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@@ -279,12 +282,12 @@
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 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
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 {
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-	return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines);
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+	return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
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 }
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 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
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 {
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-	return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
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+	return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
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 }
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 static int tc358768_calc_pll(struct tc358768_priv *priv,
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@@ -329,11 +332,15 @@
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 		u32 fbd;
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 		for (fbd = 0; fbd < 512; ++fbd) {
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-			u32 pll, diff;
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+			u32 pll, diff, pll_in;
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 			pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
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 			if (pll >= max_pll || pll < min_pll)
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+				continue;
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+
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+			pll_in = (u32)div_u64((u64)refclk, prd + 1);
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+			if (pll_in < 4000000)
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 				continue;
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 			diff = max(pll, target_pll) - min(pll, target_pll);
..
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@@ -417,6 +424,7 @@
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 	priv->output.panel = panel;
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 	priv->dsi_lanes = dev->lanes;
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+	priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
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 	/* get input ep (port0/endpoint0) */
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 	ret = -EINVAL;
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@@ -428,7 +436,7 @@
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 	}
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 	if (ret)
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-		priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format);
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+		priv->pd_lines = priv->dsi_bpp;
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 	drm_bridge_add(&priv->bridge);
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..
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@@ -626,6 +634,7 @@
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 	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
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 	struct mipi_dsi_device *dsi_dev = priv->output.dev;
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 	u32 val, val2, lptxcnt, hact, data_type;
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+	s32 raw_val;
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 	const struct drm_display_mode *mode;
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 	u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;
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 	u32 dsiclk, dsibclk;
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@@ -719,25 +728,26 @@
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 	/* 38ns < TCLK_PREPARE < 95ns */
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 	val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
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-	/* TCLK_PREPARE > 300ns */
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-	val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk),
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-				  dsibclk_nsk);
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-	val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8;
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+	/* TCLK_PREPARE + TCLK_ZERO > 300ns */
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+	val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk),
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+				  dsibclk_nsk) - 2;
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+	val |= val2 << 8;
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 	dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
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 	tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
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-	/* TCLK_TRAIL > 60ns + 3*UI */
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-	val = 60 + tc358768_to_ns(3 * ui_nsk);
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-	val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5;
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+	/* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
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+	raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 5;
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+	val = clamp(raw_val, 0, 127);
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 	dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
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 	tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
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 	/* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
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 	val = 50 + tc358768_to_ns(4 * ui_nsk);
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 	val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
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-	/* THS_ZERO > 145ns + 10*UI */
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-	val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk);
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-	val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8;
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+	/* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
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+	raw_val = tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_nsk) - 10;
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+	val2 = clamp(raw_val, 0, 127);
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+	val |= val2 << 8;
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 	dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
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 	tc358768_write(priv, TC358768_THS_HEADERCNT, val);
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@@ -753,9 +763,10 @@
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 	dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
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 	tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
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-	/* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */
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-	val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk),
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-				 dsibclk_nsk) - 5;
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+	/* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
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+	raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk),
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+				     dsibclk_nsk) - 4;
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+	val = clamp(raw_val, 0, 15);
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 	dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
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 	tc358768_write(priv, TC358768_THS_TRAILCNT, val);
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@@ -769,7 +780,7 @@
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 	/* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
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 	val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
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-	val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
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+	val = tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1;
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 	val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
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 				  dsibclk_nsk) - 2;
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 	val |= val2 << 16;
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@@ -819,8 +830,7 @@
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 	val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
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 	val |= (dsi_dev->lanes - 1) << 1;
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-	if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM))
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-		val |= TC358768_DSI_CONTROL_TXMD;
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+	val |= TC358768_DSI_CONTROL_TXMD;
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 	if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
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 		val |= TC358768_DSI_CONTROL_HSCKMD;
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@@ -866,6 +876,44 @@
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 	}
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 }
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+#define MAX_INPUT_SEL_FORMATS	1
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+
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+static u32 *
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+tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
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+				   struct drm_bridge_state *bridge_state,
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+				   struct drm_crtc_state *crtc_state,
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+				   struct drm_connector_state *conn_state,
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+				   u32 output_fmt,
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+				   unsigned int *num_input_fmts)
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+{
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+	struct tc358768_priv *priv = bridge_to_tc358768(bridge);
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+	u32 *input_fmts;
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+
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+	*num_input_fmts = 0;
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+
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+	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
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+			     GFP_KERNEL);
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+	if (!input_fmts)
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+		return NULL;
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+
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+	switch (priv->pd_lines) {
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+	case 16:
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+		input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16;
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+		break;
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+	case 18:
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+		input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18;
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+		break;
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+	default:
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+	case 24:
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+		input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
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+		break;
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+	};
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+
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+	*num_input_fmts = MAX_INPUT_SEL_FORMATS;
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+
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+	return input_fmts;
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+}
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+
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 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
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 	.attach = tc358768_bridge_attach,
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 	.mode_valid = tc358768_bridge_mode_valid,
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@@ -873,6 +921,11 @@
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 	.enable = tc358768_bridge_enable,
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 	.disable = tc358768_bridge_disable,
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 	.post_disable = tc358768_bridge_post_disable,
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+
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+	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
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+	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
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+	.atomic_reset = drm_atomic_helper_bridge_reset,
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+	.atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts,
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 };
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 static const struct drm_bridge_timings default_tc358768_timings = {