update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/bridge/adv7511/adv7533.c
..
..
@@ -100,26 +100,24 @@
100
100
 	regmap_write(adv->regmap_cec, 0x27, 0x0b);
101
101
 }
102
102
 
103
-void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode *mode)
103
+enum drm_mode_status adv7533_mode_valid(struct adv7511 *adv,
104
+					const struct drm_display_mode *mode)
104
105
 {
106
+	unsigned long max_lane_freq;
105
107
 	struct mipi_dsi_device *dsi = adv->dsi;
106
-	int lanes, ret;
108
+	u8 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
107
109
 
108
-	if (adv->num_dsi_lanes != 4)
109
-		return;
110
+	/* Check max clock for either 7533 or 7535 */
111
+	if (mode->clock > (adv->type == ADV7533 ? 80000 : 148500))
112
+		return MODE_CLOCK_HIGH;
110
113
 
111
-	if (mode->clock > 80000)
112
-		lanes = 4;
113
-	else
114
-		lanes = 3;
114
+	/* Check max clock for each lane */
115
+	max_lane_freq = (adv->type == ADV7533 ? 800000 : 891000);
115
116
 
116
-	if (lanes != dsi->lanes) {
117
-		mipi_dsi_detach(dsi);
118
-		dsi->lanes = lanes;
119
-		ret = mipi_dsi_attach(dsi);
120
-		if (ret)
121
-			dev_err(&dsi->dev, "failed to change host lanes\n");
122
-	}
117
+	if (mode->clock * bpp > max_lane_freq * adv->num_dsi_lanes)
118
+		return MODE_CLOCK_HIGH;
119
+
120
+	return MODE_OK;
123
121
 }
124
122
 
125
123
 int adv7533_patch_registers(struct adv7511 *adv)