update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
..
..
@@ -31,10 +31,10 @@
31
31
 #define TO_DCN10_LINK_ENC(link_encoder)\
32
32
 	container_of(link_encoder, struct dcn10_link_encoder, base)
33
33
 
34
-
35
34
 #define AUX_REG_LIST(id)\
36
35
 	SRI(AUX_CONTROL, DP_AUX, id), \
37
-	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
36
+	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
37
+	SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
38
38
 
39
39
 #define HPD_REG_LIST(id)\
40
40
 	SRI(DC_HPD_CONTROL, HPD, id)
..
..
@@ -62,16 +62,18 @@
62
62
 	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
63
63
 	SRI(DP_SEC_CNTL1, DP, id), \
64
64
 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
65
-	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
66
65
 	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
67
66
 
68
67
 
69
68
 #define LE_DCN10_REG_LIST(id)\
69
+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
70
70
 	LE_DCN_COMMON_REG_LIST(id)
71
71
 
72
72
 struct dcn10_link_enc_aux_registers {
73
73
 	uint32_t AUX_CONTROL;
74
74
 	uint32_t AUX_DPHY_RX_CONTROL0;
75
+	uint32_t AUX_DPHY_TX_CONTROL;
76
+	uint32_t AUX_DPHY_RX_CONTROL1;
75
77
 };
76
78
 
77
79
 struct dcn10_link_enc_hpd_registers {
..
..
@@ -103,6 +105,61 @@
103
105
 	uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
104
106
 	uint32_t DP_SEC_CNTL1;
105
107
 	uint32_t TMDS_CTL_BITS;
108
+	/* DCCG  */
109
+	uint32_t CLOCK_ENABLE;
110
+	/* DIG */
111
+	uint32_t DIG_LANE_ENABLE;
112
+	/* UNIPHY */
113
+	uint32_t CHANNEL_XBAR_CNTL;
114
+	/* DPCS */
115
+	uint32_t RDPCSTX_PHY_CNTL3;
116
+	uint32_t RDPCSTX_PHY_CNTL4;
117
+	uint32_t RDPCSTX_PHY_CNTL5;
118
+	uint32_t RDPCSTX_PHY_CNTL6;
119
+	uint32_t RDPCSTX_PHY_CNTL7;
120
+	uint32_t RDPCSTX_PHY_CNTL8;
121
+	uint32_t RDPCSTX_PHY_CNTL9;
122
+	uint32_t RDPCSTX_PHY_CNTL10;
123
+	uint32_t RDPCSTX_PHY_CNTL11;
124
+	uint32_t RDPCSTX_PHY_CNTL12;
125
+	uint32_t RDPCSTX_PHY_CNTL13;
126
+	uint32_t RDPCSTX_PHY_CNTL14;
127
+	uint32_t RDPCSTX_PHY_CNTL15;
128
+	uint32_t RDPCSTX_CNTL;
129
+	uint32_t RDPCSTX_CLOCK_CNTL;
130
+	uint32_t RDPCSTX_PHY_CNTL0;
131
+	uint32_t RDPCSTX_PHY_CNTL2;
132
+	uint32_t RDPCSTX_PLL_UPDATE_DATA;
133
+	uint32_t RDPCS_TX_CR_ADDR;
134
+	uint32_t RDPCS_TX_CR_DATA;
135
+	uint32_t DPCSTX_TX_CLOCK_CNTL;
136
+	uint32_t DPCSTX_TX_CNTL;
137
+	uint32_t RDPCSTX_INTERRUPT_CONTROL;
138
+	uint32_t RDPCSTX_PHY_FUSE0;
139
+	uint32_t RDPCSTX_PHY_FUSE1;
140
+	uint32_t RDPCSTX_PHY_FUSE2;
141
+	uint32_t RDPCSTX_PHY_FUSE3;
142
+	uint32_t RDPCSTX_PHY_RX_LD_VAL;
143
+	uint32_t DPCSTX_DEBUG_CONFIG;
144
+	uint32_t RDPCSTX_DEBUG_CONFIG;
145
+	uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
146
+	uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
147
+	uint32_t DCIO_SOFT_RESET;
148
+	/* indirect registers */
149
+	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
150
+	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
151
+	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
152
+	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
153
+	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
154
+	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
155
+	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
156
+	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
157
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
158
+	uint32_t TMDS_DCBALANCER_CONTROL;
159
+	uint32_t PHYA_LINK_CNTL2;
160
+	uint32_t PHYB_LINK_CNTL2;
161
+	uint32_t PHYC_LINK_CNTL2;
162
+#endif
106
163
 };
107
164
 
108
165
 #define LE_SF(reg_name, field_name, post_fix)\
..
..
@@ -208,12 +265,198 @@
208
265
 	type AUX_LS_READ_EN;\
209
266
 	type AUX_RX_RECEIVE_WINDOW
210
267
 
268
+
269
+#define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
270
+		type RDPCS_PHY_DP_TX0_DATA_EN;\
271
+		type RDPCS_PHY_DP_TX1_DATA_EN;\
272
+		type RDPCS_PHY_DP_TX2_DATA_EN;\
273
+		type RDPCS_PHY_DP_TX3_DATA_EN;\
274
+		type RDPCS_PHY_DP_TX0_PSTATE;\
275
+		type RDPCS_PHY_DP_TX1_PSTATE;\
276
+		type RDPCS_PHY_DP_TX2_PSTATE;\
277
+		type RDPCS_PHY_DP_TX3_PSTATE;\
278
+		type RDPCS_PHY_DP_TX0_MPLL_EN;\
279
+		type RDPCS_PHY_DP_TX1_MPLL_EN;\
280
+		type RDPCS_PHY_DP_TX2_MPLL_EN;\
281
+		type RDPCS_PHY_DP_TX3_MPLL_EN;\
282
+		type RDPCS_TX_FIFO_LANE0_EN;\
283
+		type RDPCS_TX_FIFO_LANE1_EN;\
284
+		type RDPCS_TX_FIFO_LANE2_EN;\
285
+		type RDPCS_TX_FIFO_LANE3_EN;\
286
+		type RDPCS_EXT_REFCLK_EN;\
287
+		type RDPCS_TX_FIFO_EN;\
288
+		type UNIPHY_LINK_ENABLE;\
289
+		type UNIPHY_CHANNEL0_XBAR_SOURCE;\
290
+		type UNIPHY_CHANNEL1_XBAR_SOURCE;\
291
+		type UNIPHY_CHANNEL2_XBAR_SOURCE;\
292
+		type UNIPHY_CHANNEL3_XBAR_SOURCE;\
293
+		type UNIPHY_CHANNEL0_INVERT;\
294
+		type UNIPHY_CHANNEL1_INVERT;\
295
+		type UNIPHY_CHANNEL2_INVERT;\
296
+		type UNIPHY_CHANNEL3_INVERT;\
297
+		type UNIPHY_LINK_ENABLE_HPD_MASK;\
298
+		type UNIPHY_LANE_STAGGER_DELAY;\
299
+		type RDPCS_SRAMCLK_BYPASS;\
300
+		type RDPCS_SRAMCLK_EN;\
301
+		type RDPCS_SRAMCLK_CLOCK_ON;\
302
+		type DPCS_TX_FIFO_EN;\
303
+		type RDPCS_PHY_DP_TX0_DISABLE;\
304
+		type RDPCS_PHY_DP_TX1_DISABLE;\
305
+		type RDPCS_PHY_DP_TX2_DISABLE;\
306
+		type RDPCS_PHY_DP_TX3_DISABLE;\
307
+		type RDPCS_PHY_DP_TX0_CLK_RDY;\
308
+		type RDPCS_PHY_DP_TX1_CLK_RDY;\
309
+		type RDPCS_PHY_DP_TX2_CLK_RDY;\
310
+		type RDPCS_PHY_DP_TX3_CLK_RDY;\
311
+		type RDPCS_PHY_DP_TX0_REQ;\
312
+		type RDPCS_PHY_DP_TX1_REQ;\
313
+		type RDPCS_PHY_DP_TX2_REQ;\
314
+		type RDPCS_PHY_DP_TX3_REQ;\
315
+		type RDPCS_PHY_DP_TX0_ACK;\
316
+		type RDPCS_PHY_DP_TX1_ACK;\
317
+		type RDPCS_PHY_DP_TX2_ACK;\
318
+		type RDPCS_PHY_DP_TX3_ACK;\
319
+		type RDPCS_PHY_DP_TX0_RESET;\
320
+		type RDPCS_PHY_DP_TX1_RESET;\
321
+		type RDPCS_PHY_DP_TX2_RESET;\
322
+		type RDPCS_PHY_DP_TX3_RESET;\
323
+		type RDPCS_PHY_RESET;\
324
+		type RDPCS_PHY_CR_MUX_SEL;\
325
+		type RDPCS_PHY_REF_RANGE;\
326
+		type RDPCS_PHY_DP4_POR;\
327
+		type RDPCS_SRAM_BYPASS;\
328
+		type RDPCS_SRAM_EXT_LD_DONE;\
329
+		type RDPCS_PHY_DP_TX0_TERM_CTRL;\
330
+		type RDPCS_PHY_DP_TX1_TERM_CTRL;\
331
+		type RDPCS_PHY_DP_TX2_TERM_CTRL;\
332
+		type RDPCS_PHY_DP_TX3_TERM_CTRL;\
333
+		type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
334
+		type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
335
+		type RDPCS_PHY_DP_MPLLB_SSC_EN;\
336
+		type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
337
+		type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
338
+		type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
339
+		type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
340
+		type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
341
+		type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
342
+		type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
343
+		type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
344
+		type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
345
+		type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
346
+		type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
347
+		type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
348
+		type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
349
+		type RDPCS_PHY_TX_VBOOST_LVL;\
350
+		type RDPCS_PHY_HDMIMODE_ENABLE;\
351
+		type RDPCS_PHY_DP_REF_CLK_EN;\
352
+		type RDPCS_PLL_UPDATE_DATA;\
353
+		type RDPCS_SRAM_INIT_DONE;\
354
+		type RDPCS_TX_CR_ADDR;\
355
+		type RDPCS_TX_CR_DATA;\
356
+		type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
357
+		type RDPCS_PHY_DP_MPLLB_STATE;\
358
+		type RDPCS_PHY_DP_TX0_WIDTH;\
359
+		type RDPCS_PHY_DP_TX0_RATE;\
360
+		type RDPCS_PHY_DP_TX1_WIDTH;\
361
+		type RDPCS_PHY_DP_TX1_RATE;\
362
+		type RDPCS_PHY_DP_TX2_WIDTH;\
363
+		type RDPCS_PHY_DP_TX2_RATE;\
364
+		type RDPCS_PHY_DP_TX3_WIDTH;\
365
+		type RDPCS_PHY_DP_TX3_RATE;\
366
+		type DPCS_SYMCLK_CLOCK_ON;\
367
+		type DPCS_SYMCLK_GATE_DIS;\
368
+		type DPCS_SYMCLK_EN;\
369
+		type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
370
+		type RDPCS_SYMCLK_DIV2_GATE_DIS;\
371
+		type RDPCS_SYMCLK_DIV2_EN;\
372
+		type DPCS_TX_DATA_SWAP;\
373
+		type DPCS_TX_DATA_ORDER_INVERT;\
374
+		type DPCS_TX_FIFO_RD_START_DELAY;\
375
+		type RDPCS_TX_FIFO_RD_START_DELAY;\
376
+		type RDPCS_REG_FIFO_ERROR_MASK;\
377
+		type RDPCS_TX_FIFO_ERROR_MASK;\
378
+		type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
379
+		type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
380
+		type RDPCS_PHY_DPALT_DP4;\
381
+		type RDPCS_PHY_DPALT_DISABLE;\
382
+		type RDPCS_PHY_DPALT_DISABLE_ACK;\
383
+		type RDPCS_PHY_DP_MPLLB_V2I;\
384
+		type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
385
+		type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
386
+		type RDPCS_PHY_RX_VREF_CTRL;\
387
+		type RDPCS_PHY_DP_MPLLB_CP_INT;\
388
+		type RDPCS_PHY_DP_MPLLB_CP_PROP;\
389
+		type RDPCS_PHY_RX_REF_LD_VAL;\
390
+		type RDPCS_PHY_RX_VCO_LD_VAL;\
391
+		type DPCSTX_DEBUG_CONFIG; \
392
+		type RDPCSTX_DEBUG_CONFIG; \
393
+		type RDPCS_PHY_DP_TX0_EQ_MAIN;\
394
+		type RDPCS_PHY_DP_TX0_EQ_PRE;\
395
+		type RDPCS_PHY_DP_TX0_EQ_POST;\
396
+		type RDPCS_PHY_DP_TX1_EQ_MAIN;\
397
+		type RDPCS_PHY_DP_TX1_EQ_PRE;\
398
+		type RDPCS_PHY_DP_TX1_EQ_POST;\
399
+		type RDPCS_PHY_DP_TX2_EQ_MAIN;\
400
+		type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
401
+		type RDPCS_PHY_DP_TX2_EQ_PRE;\
402
+		type RDPCS_PHY_DP_TX2_EQ_POST;\
403
+		type RDPCS_PHY_DP_TX3_EQ_MAIN;\
404
+		type RDPCS_PHY_DCO_RANGE;\
405
+		type RDPCS_PHY_DCO_FINETUNE;\
406
+		type RDPCS_PHY_DP_TX3_EQ_PRE;\
407
+		type RDPCS_PHY_DP_TX3_EQ_POST;\
408
+		type RDPCS_PHY_SUP_PRE_HP;\
409
+		type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
410
+		type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
411
+		type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
412
+		type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
413
+		type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
414
+		type UNIPHYA_SOFT_RESET;\
415
+		type UNIPHYB_SOFT_RESET;\
416
+		type UNIPHYC_SOFT_RESET;\
417
+		type UNIPHYD_SOFT_RESET;\
418
+		type UNIPHYE_SOFT_RESET;\
419
+		type UNIPHYF_SOFT_RESET
420
+
421
+#define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
422
+	type DIG_LANE0EN;\
423
+	type DIG_LANE1EN;\
424
+	type DIG_LANE2EN;\
425
+	type DIG_LANE3EN;\
426
+	type DIG_CLK_EN;\
427
+	type SYMCLKA_CLOCK_ENABLE;\
428
+	type DPHY_FEC_EN;\
429
+	type DPHY_FEC_READY_SHADOW;\
430
+	type DPHY_FEC_ACTIVE_STATUS;\
431
+	DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
432
+	type VCO_LD_VAL_OVRD;\
433
+	type VCO_LD_VAL_OVRD_EN;\
434
+	type REF_LD_VAL_OVRD;\
435
+	type REF_LD_VAL_OVRD_EN;\
436
+	type AUX_RX_START_WINDOW; \
437
+	type AUX_RX_HALF_SYM_DETECT_LEN; \
438
+	type AUX_RX_TRANSITION_FILTER_EN; \
439
+	type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
440
+	type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
441
+	type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
442
+	type AUX_RX_PHASE_DETECT_LEN; \
443
+	type AUX_RX_DETECTION_THRESHOLD; \
444
+	type AUX_TX_PRECHARGE_LEN; \
445
+	type AUX_TX_PRECHARGE_SYMBOLS; \
446
+	type AUX_MODE_DET_CHECK_DELAY;\
447
+	type DPCS_DBG_CBUS_DIS;\
448
+	type AUX_RX_PRECHARGE_SKIP;\
449
+	type AUX_RX_TIMEOUT_LEN;\
450
+	type AUX_RX_TIMEOUT_LEN_MUL
451
+
211
452
 struct dcn10_link_enc_shift {
212
453
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
454
+	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
213
455
 };
214
456
 
215
457
 struct dcn10_link_enc_mask {
216
458
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
459
+	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
217
460
 };
218
461
 
219
462
 struct dcn10_link_encoder {
..
..
@@ -271,7 +514,7 @@
271
514
 	struct link_encoder *enc,
272
515
 	enum signal_type signal);
273
516
 
274
-void configure_encoder(
517
+void enc1_configure_encoder(
275
518
 	struct dcn10_link_encoder *enc10,
276
519
 	const struct dc_link_settings *link_settings);
277
520
 
..
..
@@ -336,6 +579,13 @@
336
579
 
337
580
 bool dcn10_is_dig_enabled(struct link_encoder *enc);
338
581
 
582
+unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
583
+
339
584
 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
340
585
 
586
+enum signal_type dcn10_get_dig_mode(
587
+	struct link_encoder *enc);
588
+
589
+void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
590
+	struct dc_link_settings *link_settings);
341
591
 #endif /* __DC_LINK_ENCODER__DCN10_H__ */