forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
....@@ -23,6 +23,9 @@
2323  *
2424  */
2525 
26
+#include <linux/delay.h>
27
+#include <linux/slab.h>
28
+
2629 #include "reg_helper.h"
2730 
2831 #include "core_types.h"
....@@ -85,7 +88,10 @@
8588 	.enable_hpd = dcn10_link_encoder_enable_hpd,
8689 	.disable_hpd = dcn10_link_encoder_disable_hpd,
8790 	.is_dig_enabled = dcn10_is_dig_enabled,
88
-	.destroy = dcn10_link_encoder_destroy
91
+	.get_dig_frontend = dcn10_get_dig_frontend,
92
+	.get_dig_mode = dcn10_get_dig_mode,
93
+	.destroy = dcn10_link_encoder_destroy,
94
+	.get_max_link_cap = dcn10_link_encoder_get_max_link_cap,
8995 };
9096 
9197 static enum bp_result link_transmitter_control(
....@@ -228,7 +234,9 @@
228234 {
229235 	uint32_t value;
230236 
231
-	ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
237
+	if (!REG(DP_DPHY_INTERNAL_CTRL))
238
+		return;
239
+
232240 	value = REG_READ(DP_DPHY_INTERNAL_CTRL);
233241 
234242 	switch (panel_mode) {
....@@ -440,7 +448,46 @@
440448 	}
441449 }
442450 
443
-void configure_encoder(
451
+unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
452
+{
453
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
454
+	int32_t value;
455
+	enum engine_id result;
456
+
457
+	REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
458
+
459
+	switch (value) {
460
+	case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
461
+		result = ENGINE_ID_DIGA;
462
+		break;
463
+	case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
464
+		result = ENGINE_ID_DIGB;
465
+		break;
466
+	case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
467
+		result = ENGINE_ID_DIGC;
468
+		break;
469
+	case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
470
+		result = ENGINE_ID_DIGD;
471
+		break;
472
+	case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
473
+		result = ENGINE_ID_DIGE;
474
+		break;
475
+	case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
476
+		result = ENGINE_ID_DIGF;
477
+		break;
478
+	case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
479
+		result = ENGINE_ID_DIGG;
480
+		break;
481
+	default:
482
+		// invalid source select DIG
483
+		result = ENGINE_ID_UNKNOWN;
484
+	}
485
+
486
+	return result;
487
+
488
+}
489
+
490
+void enc1_configure_encoder(
444491 	struct dcn10_link_encoder *enc10,
445492 	const struct dc_link_settings *link_settings)
446493 {
....@@ -543,12 +590,12 @@
543590 	if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
544591 		connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
545592 		signal != SIGNAL_TYPE_HDMI_TYPE_A &&
546
-		crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
593
+		crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
547594 		return false;
548
-	if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
595
+	if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
549596 		return false;
550597 
551
-	if (crtc_timing->pix_clk_khz > max_pixel_clock)
598
+	if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
552599 		return false;
553600 
554601 	/* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
....@@ -571,30 +618,36 @@
571618 static bool dcn10_link_encoder_validate_hdmi_output(
572619 	const struct dcn10_link_encoder *enc10,
573620 	const struct dc_crtc_timing *crtc_timing,
574
-	int adjusted_pix_clk_khz)
621
+	const struct dc_edid_caps *edid_caps,
622
+	int adjusted_pix_clk_100hz)
575623 {
576624 	enum dc_color_depth max_deep_color =
577625 			enc10->base.features.max_hdmi_deep_color;
626
+
627
+	// check pixel clock against edid specified max TMDS clk
628
+	if (edid_caps->max_tmds_clk_mhz != 0 &&
629
+			adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
630
+		return false;
578631 
579632 	if (max_deep_color < crtc_timing->display_color_depth)
580633 		return false;
581634 
582635 	if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
583636 		return false;
584
-	if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
637
+	if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
585638 		return false;
586639 
587
-	if ((adjusted_pix_clk_khz == 0) ||
588
-		(adjusted_pix_clk_khz > enc10->base.features.max_hdmi_pixel_clock))
640
+	if ((adjusted_pix_clk_100hz == 0) ||
641
+		(adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
589642 		return false;
590643 
591644 	/* DCE11 HW does not support 420 */
592
-	if (!enc10->base.features.ycbcr420_supported &&
645
+	if (!enc10->base.features.hdmi_ycbcr420_supported &&
593646 			crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
594647 		return false;
595648 
596649 	if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
597
-		adjusted_pix_clk_khz >= 300000)
650
+		adjusted_pix_clk_100hz >= 3000000)
598651 		return false;
599652 	if (enc10->base.ctx->dc->debug.hdmi20_disable &&
600653 		crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
....@@ -606,22 +659,12 @@
606659 	const struct dcn10_link_encoder *enc10,
607660 	const struct dc_crtc_timing *crtc_timing)
608661 {
609
-	/* default RGB only */
610
-	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
611
-		return true;
662
+	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
663
+		if (!enc10->base.features.dp_ycbcr420_supported)
664
+			return false;
665
+	}
612666 
613
-	if (enc10->base.features.flags.bits.IS_YCBCR_CAPABLE)
614
-		return true;
615
-
616
-	/* for DCE 8.x or later DP Y-only feature,
617
-	 * we need ASIC cap + FeatureSupportDPYonly, not support 666
618
-	 */
619
-	if (crtc_timing->flags.Y_ONLY &&
620
-		enc10->base.features.flags.bits.IS_YCBCR_CAPABLE &&
621
-		crtc_timing->display_color_depth != COLOR_DEPTH_666)
622
-		return true;
623
-
624
-	return false;
667
+	return true;
625668 }
626669 
627670 void dcn10_link_encoder_construct(
....@@ -726,6 +769,8 @@
726769 		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
727770 				bp_cap_info.DP_HBR3_EN;
728771 		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
772
+		enc10->base.features.flags.bits.DP_IS_USB_C =
773
+				bp_cap_info.DP_IS_USB_C;
729774 	} else {
730775 		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
731776 				__func__,
....@@ -743,12 +788,17 @@
743788 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
744789 	bool is_valid;
745790 
791
+	//if SCDC (340-600MHz) is disabled, set to HDMI 1.4 timing limit
792
+	if (stream->sink->edid_caps.panel_patch.skip_scdc_overwrite &&
793
+		enc10->base.features.max_hdmi_pixel_clock > 300000)
794
+		enc10->base.features.max_hdmi_pixel_clock = 300000;
795
+
746796 	switch (stream->signal) {
747797 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
748798 	case SIGNAL_TYPE_DVI_DUAL_LINK:
749799 		is_valid = dcn10_link_encoder_validate_dvi_output(
750800 			enc10,
751
-			stream->sink->link->connector_signal,
801
+			stream->link->connector_signal,
752802 			stream->signal,
753803 			&stream->timing);
754804 	break;
....@@ -756,7 +806,8 @@
756806 		is_valid = dcn10_link_encoder_validate_hdmi_output(
757807 				enc10,
758808 				&stream->timing,
759
-				stream->phy_pix_clk);
809
+				&stream->sink->edid_caps,
810
+				stream->phy_pix_clk * 10);
760811 	break;
761812 	case SIGNAL_TYPE_DISPLAY_PORT:
762813 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
....@@ -920,7 +971,7 @@
920971 	 * but it's not passed to asic_control.
921972 	 * We need to set number of lanes manually.
922973 	 */
923
-	configure_encoder(enc10, link_settings);
974
+	enc1_configure_encoder(enc10, link_settings);
924975 
925976 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
926977 	cntl.engine_id = enc->preferred_engine;
....@@ -959,7 +1010,7 @@
9591010 	 * but it's not passed to asic_control.
9601011 	 * We need to set number of lanes manually.
9611012 	 */
962
-	configure_encoder(enc10, link_settings);
1013
+	enc1_configure_encoder(enc10, link_settings);
9631014 
9641015 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
9651016 	cntl.engine_id = ENGINE_ID_UNKNOWN;
....@@ -1304,7 +1355,6 @@
13041355 #define HPD_REG_UPDATE_N(reg_name, n, ...)	\
13051356 		generic_reg_update_ex(CTX, \
13061357 				HPD_REG(reg_name), \
1307
-				HPD_REG_READ(reg_name), \
13081358 				n, __VA_ARGS__)
13091359 
13101360 #define HPD_REG_UPDATE(reg_name, field, val)	\
....@@ -1327,7 +1377,6 @@
13271377 			DC_HPD_EN, 0);
13281378 }
13291379 
1330
-
13311380 #define AUX_REG(reg)\
13321381 	(enc10->aux_regs->reg)
13331382 
....@@ -1337,7 +1386,6 @@
13371386 #define AUX_REG_UPDATE_N(reg_name, n, ...)	\
13381387 		generic_reg_update_ex(CTX, \
13391388 				AUX_REG(reg_name), \
1340
-				AUX_REG_READ(reg_name), \
13411389 				n, __VA_ARGS__)
13421390 
13431391 #define AUX_REG_UPDATE(reg_name, field, val)	\
....@@ -1359,5 +1407,43 @@
13591407 
13601408 	/* 1/4 window (the maximum allowed) */
13611409 	AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
1362
-			AUX_RX_RECEIVE_WINDOW, 1);
1410
+			AUX_RX_RECEIVE_WINDOW, 0);
1411
+}
1412
+
1413
+enum signal_type dcn10_get_dig_mode(
1414
+	struct link_encoder *enc)
1415
+{
1416
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1417
+	uint32_t value;
1418
+	REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
1419
+	switch (value) {
1420
+	case 1:
1421
+		return SIGNAL_TYPE_DISPLAY_PORT;
1422
+	case 2:
1423
+		return SIGNAL_TYPE_DVI_SINGLE_LINK;
1424
+	case 3:
1425
+		return SIGNAL_TYPE_HDMI_TYPE_A;
1426
+	case 5:
1427
+		return SIGNAL_TYPE_DISPLAY_PORT_MST;
1428
+	default:
1429
+		return SIGNAL_TYPE_NONE;
1430
+	}
1431
+	return SIGNAL_TYPE_NONE;
1432
+}
1433
+
1434
+void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
1435
+	struct dc_link_settings *link_settings)
1436
+{
1437
+	/* Set Default link settings */
1438
+	struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1439
+			LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
1440
+
1441
+	/* Higher link settings based on feature supported */
1442
+	if (enc->features.flags.bits.IS_HBR2_CAPABLE)
1443
+		max_link_cap.link_rate = LINK_RATE_HIGH2;
1444
+
1445
+	if (enc->features.flags.bits.IS_HBR3_CAPABLE)
1446
+		max_link_cap.link_rate = LINK_RATE_HIGH3;
1447
+
1448
+	*link_settings = max_link_cap;
13631449 }