update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
..
..
@@ -91,18 +91,13 @@
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 	DSCL_MODE_DSCL_BYPASS = 6
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 };
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-enum gamut_remap_select {
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-	GAMUT_REMAP_BYPASS = 0,
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-	GAMUT_REMAP_COEFF,
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-	GAMUT_REMAP_COMA_COEFF,
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-	GAMUT_REMAP_COMB_COEFF
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-};
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-
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 void dpp_read_state(struct dpp *dpp_base,
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 		struct dcn_dpp_state *s)
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 {
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 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
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+	REG_GET(DPP_CONTROL,
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+			DPP_CLOCK_ENABLE, &s->is_enabled);
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 	REG_GET(CM_IGAM_CONTROL,
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 			CM_IGAM_LUT_MODE, &s->igam_lut_mode);
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 	REG_GET(CM_IGAM_CONTROL,
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@@ -114,12 +109,14 @@
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 	REG_GET(CM_GAMUT_REMAP_CONTROL,
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 			CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
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-	s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
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-	s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
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-	s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
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-	s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
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-	s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
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-	s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
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+	if (s->gamut_remap_mode) {
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+		s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
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+		s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
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+		s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
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+		s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
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+		s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
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+		s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
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+	}
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 }
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 /* Program gamut remap in bypass mode */
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@@ -132,18 +129,11 @@
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 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
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-static bool dpp_get_optimal_number_of_taps(
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+bool dpp1_get_optimal_number_of_taps(
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 		struct dpp *dpp,
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 		struct scaler_data *scl_data,
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 		const struct scaling_taps *in_taps)
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 {
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-	uint32_t pixel_width;
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-
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-	if (scl_data->viewport.width > scl_data->recout.width)
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-		pixel_width = scl_data->recout.width;
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-	else
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-		pixel_width = scl_data->viewport.width;
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-
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 	/* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
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 	if (scl_data->format == PIXEL_FORMAT_FP16 &&
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 		dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
..
..
@@ -293,7 +283,8 @@
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 		enum surface_pixel_format format,
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 		enum expansion_mode mode,
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 		struct dc_csc_transform input_csc_color_matrix,
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-		enum dc_color_space input_color_space)
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+		enum dc_color_space input_color_space,
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+		struct cnv_alpha_2bit_lut *alpha_2bit_lut)
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 {
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 	uint32_t pixel_format;
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 	uint32_t alpha_en;
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@@ -424,8 +415,9 @@
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 void dpp1_set_cursor_attributes(
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 		struct dpp *dpp_base,
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-		enum dc_cursor_color_format color_format)
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+		struct dc_cursor_attributes *cursor_attributes)
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 {
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+	enum dc_cursor_color_format color_format = cursor_attributes->color_format;
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 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
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 	REG_UPDATE_2(CURSOR0_CONTROL,
..
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@@ -446,17 +438,38 @@
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 		struct dpp *dpp_base,
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 		const struct dc_cursor_position *pos,
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 		const struct dc_cursor_mi_param *param,
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-		uint32_t width)
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+		uint32_t width,
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+		uint32_t height)
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 {
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 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
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 	int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
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+	int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
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 	uint32_t cur_en = pos->enable ? 1 : 0;
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+
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+	// Cursor width/height and hotspots need to be rotated for offset calculation
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+	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
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+		swap(width, height);
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+		if (param->rotation == ROTATION_ANGLE_90) {
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+			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
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+			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
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+		}
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+	} else if (param->rotation == ROTATION_ANGLE_180) {
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+		src_x_offset = pos->x - param->viewport.x;
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+		src_y_offset = pos->y - param->viewport.y;
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+	}
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+
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 	if (src_x_offset >= (int)param->viewport.width)
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 		cur_en = 0;  /* not visible beyond right edge*/
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 	if (src_x_offset + (int)width <= 0)
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 		cur_en = 0;  /* not visible beyond left edge*/
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+
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+	if (src_y_offset >= (int)param->viewport.height)
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+		cur_en = 0;  /* not visible beyond bottom edge*/
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+
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+	if (src_y_offset + (int)height <= 0)
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+		cur_en = 0;  /* not visible beyond top edge*/
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 	REG_UPDATE(CURSOR0_CONTROL,
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 			CUR0_ENABLE, cur_en);
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@@ -497,7 +510,7 @@
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 		.dpp_read_state = dpp_read_state,
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 		.dpp_reset = dpp_reset,
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 		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
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-		.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
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+		.dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
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 		.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
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 		.dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
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 		.dpp_set_csc_default = dpp1_cm_set_output_csc_default,
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@@ -518,6 +531,9 @@
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 		.set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
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 		.dpp_dppclk_control = dpp1_dppclk_control,
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 		.dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
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+		.dpp_program_blnd_lut = NULL,
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+		.dpp_program_shaper_lut = NULL,
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+		.dpp_program_3dlut = NULL
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 };
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 static struct dpp_caps dcn10_dpp_cap = {