update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
..
..
@@ -36,34 +36,6 @@
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 #include "dce/dce_8_0_d.h"
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 #include "dce/dce_8_0_sh_mask.h"
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-struct dce80_hw_seq_reg_offsets {
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-	uint32_t crtc;
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-};
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-
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-static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
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-{
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-	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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-},
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-{
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-	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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-},
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-{
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-	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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-},
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-{
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-	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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-},
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-{
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-	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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-},
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-{
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-	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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-}
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-};
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-
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-#define HW_REG_CRTC(reg, id)\
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-	(reg + reg_offsets[id].crtc)
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-
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 /*******************************************************************************
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  * Private definitions
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  ******************************************************************************/
..
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@@ -74,8 +46,9 @@
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 {
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 	dce110_hw_sequencer_construct(dc);
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-	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
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+	dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
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 	dc->hwss.pipe_control_lock = dce_pipe_control_lock;
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-	dc->hwss.set_bandwidth = dce100_set_bandwidth;
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+	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
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+	dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
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 }
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