update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
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@@ -38,7 +38,8 @@
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 #define AUX_REG_LIST(id)\
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 	SRI(AUX_CONTROL, DP_AUX, id), \
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-	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
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+	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
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+	SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
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 #define HPD_REG_LIST(id)\
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 	SRI(DC_HPD_CONTROL, HPD, id)
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@@ -75,6 +76,34 @@
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 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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 	SR(DCI_MEM_PWR_STATUS)
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define LE_DCE60_REG_LIST(id)\
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+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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+	SR(DMCU_RAM_ACCESS_CTRL), \
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+	SR(DMCU_IRAM_RD_CTRL), \
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+	SR(DMCU_IRAM_RD_DATA), \
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+	SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
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+	SRI(DIG_BE_CNTL, DIG, id), \
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+	SRI(DIG_BE_EN_CNTL, DIG, id), \
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+	SRI(DP_CONFIG, DP, id), \
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+	SRI(DP_DPHY_CNTL, DP, id), \
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+	SRI(DP_DPHY_PRBS_CNTL, DP, id), \
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+	SRI(DP_DPHY_SYM0, DP, id), \
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+	SRI(DP_DPHY_SYM1, DP, id), \
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+	SRI(DP_DPHY_SYM2, DP, id), \
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+	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
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+	SRI(DP_LINK_CNTL, DP, id), \
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+	SRI(DP_LINK_FRAMING_CNTL, DP, id), \
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+	SRI(DP_MSE_SAT0, DP, id), \
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+	SRI(DP_MSE_SAT1, DP, id), \
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+	SRI(DP_MSE_SAT2, DP, id), \
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+	SRI(DP_MSE_SAT_UPDATE, DP, id), \
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+	SRI(DP_SEC_CNTL, DP, id), \
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+	SRI(DP_VID_STREAM_CNTL, DP, id), \
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+	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
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+	SRI(DP_SEC_CNTL1, DP, id)
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+#endif
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+
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 #define LE_DCE80_REG_LIST(id)\
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 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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 	LE_COMMON_REG_LIST_BASE(id)
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@@ -107,6 +136,7 @@
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 struct dce110_link_enc_aux_registers {
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 	uint32_t AUX_CONTROL;
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 	uint32_t AUX_DPHY_RX_CONTROL0;
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+	uint32_t AUX_DPHY_RX_CONTROL1;
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 };
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 struct dce110_link_enc_hpd_registers {
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@@ -169,6 +199,16 @@
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 	const struct dce110_link_enc_aux_registers *aux_regs,
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 	const struct dce110_link_enc_hpd_registers *hpd_regs);
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+void dce60_link_encoder_construct(
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+	struct dce110_link_encoder *enc110,
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+	const struct encoder_init_data *init_data,
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+	const struct encoder_feature_support *enc_features,
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+	const struct dce110_link_enc_registers *link_regs,
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+	const struct dce110_link_enc_aux_registers *aux_regs,
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+	const struct dce110_link_enc_hpd_registers *hpd_regs);
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+#endif
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+
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 bool dce110_link_encoder_validate_dvi_output(
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 	const struct dce110_link_encoder *enc110,
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 	enum signal_type connector_signal,
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@@ -225,6 +265,12 @@
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 	const struct dc_link_settings *link_settings,
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 	enum clock_source_id clock_source);
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+/* enables LVDS PHY output */
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+void dce110_link_encoder_enable_lvds_output(
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+	struct link_encoder *enc,
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+	enum clock_source_id clock_source,
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+	uint32_t pixel_clock);
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+
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 /* disable PHY output */
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 void dce110_link_encoder_disable_output(
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 	struct link_encoder *enc,
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@@ -249,6 +295,8 @@
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 	enum engine_id engine,
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 	bool connect);
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+unsigned int dce110_get_dig_frontend(struct link_encoder *enc);
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+
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 void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
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 	struct link_encoder *enc,
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 	uint32_t index);
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@@ -265,4 +313,7 @@
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 bool dce110_is_dig_enabled(struct link_encoder *enc);
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+void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,
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+	struct dc_link_settings *link_settings);
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+
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 #endif /* __DC_LINK_ENCODER__DCE110_H__ */