update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/arm/bifrost/device/backend/mali_kbase_device_hw_jm.c
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@@ -1,7 +1,7 @@
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 // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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 /*
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  *
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- * (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
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+ * (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
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  *
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  * This program is free software and is provided to you under the terms of the
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  * GNU General Public License version 2 as published by the Free Software
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@@ -51,6 +51,7 @@
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 		address);
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 	if (multiple)
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 		dev_warn(kbdev->dev, "There were multiple GPU faults - some have not been reported\n");
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+
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 }
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 void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val)
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@@ -62,11 +63,19 @@
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 	if (val & RESET_COMPLETED)
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 		kbase_pm_reset_done(kbdev);
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+	/* Defer clearing CLEAN_CACHES_COMPLETED to kbase_clean_caches_done.
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+	 * We need to acquire hwaccess_lock to avoid a race condition with
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+	 * kbase_gpu_cache_flush_and_busy_wait
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+	 */
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+	KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val & ~CLEAN_CACHES_COMPLETED);
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+	kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val & ~CLEAN_CACHES_COMPLETED);
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+
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+	/* kbase_instr_hwcnt_sample_done frees the HWCNT pipeline to request another
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+	 * sample. Therefore this must be called after clearing the IRQ to avoid a
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+	 * race between clearing and the next sample raising the IRQ again.
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+	 */
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 	if (val & PRFCNT_SAMPLE_COMPLETED)
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 		kbase_instr_hwcnt_sample_done(kbdev);
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-
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-	KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val);
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-	kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val);
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 	/* kbase_pm_check_transitions (called by kbase_pm_power_changed) must
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 	 * be called after the IRQ has been cleared. This is because it might
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@@ -96,3 +105,39 @@
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 	KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_DONE, NULL, val);
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 }
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+
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+#if IS_ENABLED(CONFIG_MALI_REAL_HW)
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+void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value)
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+{
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+	WARN_ON(!kbdev->pm.backend.gpu_powered);
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+
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+	writel(value, kbdev->reg + offset);
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+
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+#if IS_ENABLED(CONFIG_DEBUG_FS)
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+	if (unlikely(kbdev->io_history.enabled))
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+		kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
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+				     value, 1);
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+#endif /* CONFIG_DEBUG_FS */
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+	dev_dbg(kbdev->dev, "w: reg %08x val %08x", offset, value);
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+}
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+KBASE_EXPORT_TEST_API(kbase_reg_write);
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+
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+u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset)
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+{
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+	u32 val;
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+
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+	WARN_ON(!kbdev->pm.backend.gpu_powered);
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+
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+	val = readl(kbdev->reg + offset);
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+
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+#if IS_ENABLED(CONFIG_DEBUG_FS)
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+	if (unlikely(kbdev->io_history.enabled))
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+		kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
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+				     val, 0);
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+#endif /* CONFIG_DEBUG_FS */
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+	dev_dbg(kbdev->dev, "r: reg %08x val %08x", offset, val);
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+
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+	return val;
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+}
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+KBASE_EXPORT_TEST_API(kbase_reg_read);
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+#endif /* IS_ENABLED(CONFIG_MALI_REAL_HW) */