update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/clk/x86/clk-lgm.c
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@@ -1,10 +1,12 @@
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 // SPDX-License-Identifier: GPL-2.0
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 /*
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+ * Copyright (C) 2020-2022 MaxLinear, Inc.
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  * Copyright (C) 2020 Intel Corporation.
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- * Zhu YiXin <yixin.zhu@intel.com>
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- * Rahul Tanwar <rahul.tanwar@intel.com>
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+ * Zhu Yixin <yzhu@maxlinear.com>
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+ * Rahul Tanwar <rtanwar@maxlinear.com>
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  */
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 #include <linux/clk-provider.h>
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+#include <linux/mfd/syscon.h>
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 #include <linux/of.h>
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 #include <linux/platform_device.h>
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 #include <dt-bindings/clock/intel,lgm-clk.h>
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@@ -253,8 +255,8 @@
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 	LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1,
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 		  8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2),
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 	LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0),
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-	LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR,
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-		25, 3, 0, 0, 0, 0, dcl_div),
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+	LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", CLK_SET_RATE_PARENT, CGU_PCMCR,
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+		25, 3, 0, 0, DIV_CLK_NO_MASK, 0, dcl_div),
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 	LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR,
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 		0, 1, CLK_MUX_ROUND_CLOSEST, 0),
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 	LGM_FIXED_FACTOR(LGM_CLK_DDR_PHY, "ddr_phy", "ddr",
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@@ -433,13 +435,15 @@
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 	ctx->clk_data.num = CLK_NR_CLKS;
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-	ctx->membase = devm_platform_ioremap_resource(pdev, 0);
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-	if (IS_ERR(ctx->membase))
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+	ctx->membase = syscon_node_to_regmap(np);
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+	if (IS_ERR(ctx->membase)) {
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+		dev_err(dev, "Failed to get clk CGU iomem\n");
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 		return PTR_ERR(ctx->membase);
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+	}
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+
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 	ctx->np = np;
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 	ctx->dev = dev;
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-	spin_lock_init(&ctx->lock);
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 	ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
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 				    ARRAY_SIZE(lgm_pll_clks));