update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/clk/x86/clk-cgu.h
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@@ -1,28 +1,28 @@
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 /* SPDX-License-Identifier: GPL-2.0 */
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 /*
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- * Copyright(c) 2020 Intel Corporation.
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- * Zhu YiXin <yixin.zhu@intel.com>
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- * Rahul Tanwar <rahul.tanwar@intel.com>
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+ * Copyright (C) 2020-2022 MaxLinear, Inc.
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+ * Copyright (C) 2020 Intel Corporation.
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+ * Zhu Yixin <yzhu@maxlinear.com>
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+ * Rahul Tanwar <rtanwar@maxlinear.com>
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  */
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 #ifndef __CLK_CGU_H
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 #define __CLK_CGU_H
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-#include <linux/io.h>
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+#include <linux/regmap.h>
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 struct lgm_clk_mux {
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 	struct clk_hw hw;
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-	void __iomem *membase;
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+	struct regmap *membase;
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 	unsigned int reg;
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 	u8 shift;
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 	u8 width;
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 	unsigned long flags;
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-	spinlock_t lock;
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 };
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 struct lgm_clk_divider {
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 	struct clk_hw hw;
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-	void __iomem *membase;
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+	struct regmap *membase;
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 	unsigned int reg;
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 	u8 shift;
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 	u8 width;
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@@ -30,12 +30,11 @@
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 	u8 width_gate;
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 	unsigned long flags;
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 	const struct clk_div_table *table;
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-	spinlock_t lock;
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 };
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 struct lgm_clk_ddiv {
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 	struct clk_hw hw;
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-	void __iomem *membase;
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+	struct regmap *membase;
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 	unsigned int reg;
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 	u8 shift0;
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 	u8 width0;
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@@ -48,16 +47,14 @@
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 	unsigned int mult;
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 	unsigned int div;
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 	unsigned long flags;
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-	spinlock_t lock;
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 };
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 struct lgm_clk_gate {
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 	struct clk_hw hw;
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-	void __iomem *membase;
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+	struct regmap *membase;
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 	unsigned int reg;
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 	u8 shift;
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 	unsigned long flags;
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-	spinlock_t lock;
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 };
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 enum lgm_clk_type {
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@@ -77,11 +74,10 @@
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  * @clk_data: array of hw clocks and clk number.
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  */
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 struct lgm_clk_provider {
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-	void __iomem *membase;
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+	struct regmap *membase;
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 	struct device_node *np;
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 	struct device *dev;
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 	struct clk_hw_onecell_data clk_data;
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-	spinlock_t lock;
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 };
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 enum pll_type {
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@@ -92,11 +88,10 @@
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 struct lgm_clk_pll {
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 	struct clk_hw hw;
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-	void __iomem *membase;
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+	struct regmap *membase;
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 	unsigned int reg;
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 	unsigned long flags;
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 	enum pll_type type;
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-	spinlock_t lock;
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 };
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 /**
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@@ -202,6 +197,8 @@
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 /* clock flags definition */
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 #define CLOCK_FLAG_VAL_INIT	BIT(16)
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 #define MUX_CLK_SW		BIT(17)
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+#define GATE_CLK_HW		BIT(18)
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+#define DIV_CLK_NO_MASK		BIT(19)
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 #define LGM_MUX(_id, _name, _pdata, _f, _reg,		\
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 		_shift, _width, _cf, _v)		\
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@@ -300,29 +297,32 @@
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 		.div = _d,					\
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 	}
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-static inline void lgm_set_clk_val(void __iomem *membase, u32 reg,
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+static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
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 				   u8 shift, u8 width, u32 set_val)
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 {
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 	u32 mask = (GENMASK(width - 1, 0) << shift);
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-	u32 regval;
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-	regval = readl(membase + reg);
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-	regval = (regval & ~mask) | ((set_val << shift) & mask);
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-	writel(regval, membase + reg);
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+	regmap_update_bits(membase, reg, mask, set_val << shift);
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 }
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-static inline u32 lgm_get_clk_val(void __iomem *membase, u32 reg,
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+static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg,
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 				  u8 shift, u8 width)
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 {
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 	u32 mask = (GENMASK(width - 1, 0) << shift);
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 	u32 val;
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-	val = readl(membase + reg);
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+	if (regmap_read(membase, reg, &val)) {
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+		WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg);
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+		return 0;
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+	}
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+
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 	val = (val & mask) >> shift;
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 	return val;
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 }
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+
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+
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 int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
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 			      const struct lgm_clk_branch *list,
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 			      unsigned int nr_clk);