update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/clk/x86/clk-cgu-pll.c
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@@ -1,8 +1,9 @@
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 // SPDX-License-Identifier: GPL-2.0
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 /*
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+ * Copyright (C) 2020-2022 MaxLinear, Inc.
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  * Copyright (C) 2020 Intel Corporation.
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- * Zhu YiXin <yixin.zhu@intel.com>
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- * Rahul Tanwar <rahul.tanwar@intel.com>
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+ * Zhu Yixin <yzhu@maxlinear.com>
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+ * Rahul Tanwar <rtanwar@maxlinear.com>
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  */
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 #include <linux/clk-provider.h>
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@@ -40,13 +41,10 @@
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 {
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 	struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);
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 	unsigned int div, mult, frac;
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-	unsigned long flags;
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-	spin_lock_irqsave(&pll->lock, flags);
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 	mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12);
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 	div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6);
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 	frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24);
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-	spin_unlock_irqrestore(&pll->lock, flags);
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 	if (pll->type == TYPE_LJPLL)
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 		div *= 4;
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@@ -57,12 +55,9 @@
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 static int lgm_pll_is_enabled(struct clk_hw *hw)
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 {
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 	struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);
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-	unsigned long flags;
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 	unsigned int ret;
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-	spin_lock_irqsave(&pll->lock, flags);
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 	ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1);
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-	spin_unlock_irqrestore(&pll->lock, flags);
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 	return ret;
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 }
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@@ -70,15 +65,13 @@
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 static int lgm_pll_enable(struct clk_hw *hw)
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 {
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 	struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);
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-	unsigned long flags;
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 	u32 val;
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 	int ret;
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-	spin_lock_irqsave(&pll->lock, flags);
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 	lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1);
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-	ret = readl_poll_timeout_atomic(pll->membase + pll->reg,
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-					val, (val & 0x1), 1, 100);
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-	spin_unlock_irqrestore(&pll->lock, flags);
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+	ret = regmap_read_poll_timeout_atomic(pll->membase, pll->reg,
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+					      val, (val & 0x1), 1, 100);
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+
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 	return ret;
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 }
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@@ -86,11 +79,8 @@
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 static void lgm_pll_disable(struct clk_hw *hw)
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 {
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 	struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);
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-	unsigned long flags;
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-	spin_lock_irqsave(&pll->lock, flags);
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 	lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 0);
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-	spin_unlock_irqrestore(&pll->lock, flags);
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 }
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 static const struct clk_ops lgm_pll_ops = {
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@@ -121,7 +111,6 @@
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 		return ERR_PTR(-ENOMEM);
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 	pll->membase = ctx->membase;
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-	pll->lock = ctx->lock;
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 	pll->reg = list->reg;
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 	pll->flags = list->flags;
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 	pll->type = list->type;