update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/clk/tegra/clk-tegra20.c
..
..
@@ -18,24 +18,24 @@
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 #define MISC_CLK_ENB 0x48
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 #define OSC_CTRL 0x50
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-#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
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-#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
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-#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
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-#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
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-#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
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-#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
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+#define OSC_CTRL_OSC_FREQ_MASK (3u<<30)
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+#define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30)
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+#define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30)
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+#define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30)
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+#define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30)
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+#define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK)
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-#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
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-#define OSC_CTRL_PLL_REF_DIV_1		(0<<28)
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-#define OSC_CTRL_PLL_REF_DIV_2		(1<<28)
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-#define OSC_CTRL_PLL_REF_DIV_4		(2<<28)
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+#define OSC_CTRL_PLL_REF_DIV_MASK	(3u<<28)
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+#define OSC_CTRL_PLL_REF_DIV_1		(0u<<28)
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+#define OSC_CTRL_PLL_REF_DIV_2		(1u<<28)
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+#define OSC_CTRL_PLL_REF_DIV_4		(2u<<28)
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 #define OSC_FREQ_DET 0x58
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-#define OSC_FREQ_DET_TRIG (1<<31)
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+#define OSC_FREQ_DET_TRIG (1u<<31)
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 #define OSC_FREQ_DET_STATUS 0x5c
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-#define OSC_FREQ_DET_BUSY (1<<31)
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-#define OSC_FREQ_DET_CNT_MASK 0xFFFF
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+#define OSC_FREQ_DET_BUSYu (1<<31)
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+#define OSC_FREQ_DET_CNT_MASK 0xFFFFu
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 #define TEGRA20_CLK_PERIPH_BANKS	3
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