hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/drivers/clk/qcom/gpucc-sc7180.c
....@@ -21,8 +21,6 @@
2121 #define CX_GMU_CBCR_SLEEP_SHIFT 4
2222 #define CX_GMU_CBCR_WAKE_MASK 0xF
2323 #define CX_GMU_CBCR_WAKE_SHIFT 8
24
-#define CLK_DIS_WAIT_SHIFT 12
25
-#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT)
2624
2725 enum {
2826 P_BI_TCXO,
....@@ -163,6 +161,7 @@
163161 static struct gdsc cx_gdsc = {
164162 .gdscr = 0x106c,
165163 .gds_hw_ctrl = 0x1540,
164
+ .clk_dis_wait_val = 8,
166165 .pd = {
167166 .name = "cx_gdsc",
168167 },
....@@ -244,10 +243,6 @@
244243 mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
245244 value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
246245 regmap_update_bits(regmap, 0x1098, mask, value);
247
-
248
- /* Configure clk_dis_wait for gpu_cx_gdsc */
249
- regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
250
- 8 << CLK_DIS_WAIT_SHIFT);
251246
252247 return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
253248 }