.. | .. |
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21 | 21 | #define CX_GMU_CBCR_SLEEP_SHIFT 4 |
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22 | 22 | #define CX_GMU_CBCR_WAKE_MASK 0xF |
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23 | 23 | #define CX_GMU_CBCR_WAKE_SHIFT 8 |
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24 | | -#define CLK_DIS_WAIT_SHIFT 12 |
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25 | | -#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT) |
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26 | 24 | |
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27 | 25 | enum { |
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28 | 26 | P_BI_TCXO, |
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.. | .. |
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163 | 161 | static struct gdsc cx_gdsc = { |
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164 | 162 | .gdscr = 0x106c, |
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165 | 163 | .gds_hw_ctrl = 0x1540, |
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| 164 | + .clk_dis_wait_val = 8, |
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166 | 165 | .pd = { |
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167 | 166 | .name = "cx_gdsc", |
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168 | 167 | }, |
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.. | .. |
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244 | 243 | mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; |
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245 | 244 | value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT; |
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246 | 245 | regmap_update_bits(regmap, 0x1098, mask, value); |
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247 | | - |
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248 | | - /* Configure clk_dis_wait for gpu_cx_gdsc */ |
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249 | | - regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK, |
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250 | | - 8 << CLK_DIS_WAIT_SHIFT); |
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251 | 246 | |
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252 | 247 | return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap); |
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253 | 248 | } |
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