forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/clk/qcom/gcc-sc7180.c
....@@ -285,7 +285,7 @@
285285 	.clkr.hw.init = &(struct clk_init_data){
286286 		.name = "gcc_cpuss_ahb_clk_src",
287287 		.parent_data = gcc_parent_data_0_ao,
288
-		.num_parents = 4,
288
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
289289 		.flags = CLK_SET_RATE_PARENT,
290290 		.ops = &clk_rcg2_ops,
291291 		},
....@@ -309,7 +309,7 @@
309309 	.clkr.hw.init = &(struct clk_init_data){
310310 		.name = "gcc_gp1_clk_src",
311311 		.parent_data = gcc_parent_data_4,
312
-		.num_parents = 5,
312
+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
313313 		.ops = &clk_rcg2_ops,
314314 	},
315315 };
....@@ -323,7 +323,7 @@
323323 	.clkr.hw.init = &(struct clk_init_data){
324324 		.name = "gcc_gp2_clk_src",
325325 		.parent_data = gcc_parent_data_4,
326
-		.num_parents = 5,
326
+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
327327 		.ops = &clk_rcg2_ops,
328328 	},
329329 };
....@@ -337,7 +337,7 @@
337337 	.clkr.hw.init = &(struct clk_init_data){
338338 		.name = "gcc_gp3_clk_src",
339339 		.parent_data = gcc_parent_data_4,
340
-		.num_parents = 5,
340
+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
341341 		.ops = &clk_rcg2_ops,
342342 	},
343343 };
....@@ -357,7 +357,7 @@
357357 	.clkr.hw.init = &(struct clk_init_data){
358358 		.name = "gcc_pdm2_clk_src",
359359 		.parent_data = gcc_parent_data_0,
360
-		.num_parents = 4,
360
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
361361 		.ops = &clk_rcg2_ops,
362362 	},
363363 };
....@@ -378,7 +378,7 @@
378378 	.clkr.hw.init = &(struct clk_init_data){
379379 		.name = "gcc_qspi_core_clk_src",
380380 		.parent_data = gcc_parent_data_2,
381
-		.num_parents = 6,
381
+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
382382 		.ops = &clk_rcg2_ops,
383383 	},
384384 };
....@@ -619,7 +619,7 @@
619619 	.clkr.hw.init = &(struct clk_init_data){
620620 		.name = "gcc_sdcc1_apps_clk_src",
621621 		.parent_data = gcc_parent_data_1,
622
-		.num_parents = 5,
622
+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
623623 		.ops = &clk_rcg2_floor_ops,
624624 	},
625625 };
....@@ -641,7 +641,7 @@
641641 	.clkr.hw.init = &(struct clk_init_data){
642642 		.name = "gcc_sdcc1_ice_core_clk_src",
643643 		.parent_data = gcc_parent_data_0,
644
-		.num_parents = 4,
644
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
645645 		.ops = &clk_rcg2_ops,
646646 	},
647647 };
....@@ -665,7 +665,8 @@
665665 	.clkr.hw.init = &(struct clk_init_data){
666666 		.name = "gcc_sdcc2_apps_clk_src",
667667 		.parent_data = gcc_parent_data_5,
668
-		.num_parents = 5,
668
+		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
669
+		.flags = CLK_OPS_PARENT_ENABLE,
669670 		.ops = &clk_rcg2_floor_ops,
670671 	},
671672 };
....@@ -688,7 +689,7 @@
688689 	.clkr.hw.init = &(struct clk_init_data){
689690 		.name = "gcc_ufs_phy_axi_clk_src",
690691 		.parent_data = gcc_parent_data_0,
691
-		.num_parents = 4,
692
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
692693 		.ops = &clk_rcg2_ops,
693694 	},
694695 };
....@@ -710,7 +711,7 @@
710711 	.clkr.hw.init = &(struct clk_init_data){
711712 		.name = "gcc_ufs_phy_ice_core_clk_src",
712713 		.parent_data = gcc_parent_data_0,
713
-		.num_parents = 4,
714
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
714715 		.ops = &clk_rcg2_ops,
715716 	},
716717 };
....@@ -730,7 +731,7 @@
730731 	.clkr.hw.init = &(struct clk_init_data){
731732 		.name = "gcc_ufs_phy_phy_aux_clk_src",
732733 		.parent_data = gcc_parent_data_3,
733
-		.num_parents = 3,
734
+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
734735 		.ops = &clk_rcg2_ops,
735736 	},
736737 };
....@@ -751,7 +752,7 @@
751752 	.clkr.hw.init = &(struct clk_init_data){
752753 		.name = "gcc_ufs_phy_unipro_core_clk_src",
753754 		.parent_data = gcc_parent_data_0,
754
-		.num_parents = 4,
755
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
755756 		.ops = &clk_rcg2_ops,
756757 	},
757758 };
....@@ -773,7 +774,7 @@
773774 	.clkr.hw.init = &(struct clk_init_data){
774775 		.name = "gcc_usb30_prim_master_clk_src",
775776 		.parent_data = gcc_parent_data_0,
776
-		.num_parents = 4,
777
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
777778 		.ops = &clk_rcg2_ops,
778779 	},
779780 };
....@@ -793,7 +794,7 @@
793794 	.clkr.hw.init = &(struct clk_init_data){
794795 		.name = "gcc_usb30_prim_mock_utmi_clk_src",
795796 		.parent_data = gcc_parent_data_0,
796
-		.num_parents = 4,
797
+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
797798 		.ops = &clk_rcg2_ops,
798799 	},
799800 };
....@@ -812,7 +813,7 @@
812813 	.clkr.hw.init = &(struct clk_init_data){
813814 		.name = "gcc_usb3_prim_phy_aux_clk_src",
814815 		.parent_data = gcc_parent_data_6,
815
-		.num_parents = 4,
816
+		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
816817 		.ops = &clk_rcg2_ops,
817818 	},
818819 };