.. | .. |
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90 | 90 | { |
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91 | 91 | struct _parisc_agp_info *info = &parisc_agp_info; |
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92 | 92 | |
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| 93 | + /* force fdc ops to be visible to IOMMU */ |
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| 94 | + asm_io_sync(); |
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| 95 | + |
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93 | 96 | writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM); |
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94 | 97 | readq(info->ioc_regs+IOC_PCOM); /* flush */ |
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95 | 98 | } |
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.. | .. |
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158 | 161 | info->gatt[j] = |
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159 | 162 | parisc_agp_mask_memory(agp_bridge, |
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160 | 163 | paddr, type); |
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| 164 | + asm_io_fdc(&info->gatt[j]); |
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161 | 165 | } |
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162 | 166 | } |
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163 | 167 | |
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.. | .. |
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191 | 195 | parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, |
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192 | 196 | int type) |
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193 | 197 | { |
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194 | | - return SBA_PDIR_VALID_BIT | addr; |
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| 198 | + unsigned ci; /* coherent index */ |
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| 199 | + dma_addr_t pa; |
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| 200 | + |
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| 201 | + pa = addr & IOVP_MASK; |
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| 202 | + asm("lci 0(%1), %0" : "=r" (ci) : "r" (phys_to_virt(pa))); |
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| 203 | + |
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| 204 | + pa |= (ci >> PAGE_SHIFT) & 0xff;/* move CI (8 bits) into lowest byte */ |
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| 205 | + pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ |
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| 206 | + |
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| 207 | + return cpu_to_le64(pa); |
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195 | 208 | } |
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196 | 209 | |
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197 | 210 | static void |
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.. | .. |
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381 | 394 | static int __init |
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382 | 395 | parisc_agp_init(void) |
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383 | 396 | { |
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384 | | - extern struct sba_device *sba_list; |
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385 | | - |
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386 | 397 | int err = -1; |
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387 | 398 | struct parisc_device *sba = NULL, *lba = NULL; |
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388 | 399 | struct lba_device *lbadev = NULL; |
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