update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/xtensa/include/asm/futex.h
..
..
@@ -1,11 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Atomic futex routines
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  *
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  * Based on the PowerPC implementataion
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * Copyright (C) 2013 TangoTec Ltd.
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  *
..
..
@@ -15,113 +12,152 @@
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 #ifndef _ASM_XTENSA_FUTEX_H
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 #define _ASM_XTENSA_FUTEX_H
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-#ifdef __KERNEL__
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-
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 #include <linux/futex.h>
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 #include <linux/uaccess.h>
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 #include <linux/errno.h>
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-#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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+#if XCHAL_HAVE_EXCLUSIVE
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+#define __futex_atomic_op(insn, ret, old, uaddr, arg)	\
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 	__asm__ __volatile(				\
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-	"1:	l32i	%0, %2, 0\n"			\
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+	"1:	l32ex	%[oldval], %[addr]\n"		\
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 		insn "\n"				\
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-	"	wsr	%0, scompare1\n"		\
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-	"2:	s32c1i	%1, %2, 0\n"			\
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-	"	bne	%1, %0, 1b\n"			\
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-	"	movi	%1, 0\n"			\
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+	"2:	s32ex	%[newval], %[addr]\n"		\
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+	"	getex	%[newval]\n"			\
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+	"	beqz	%[newval], 1b\n"		\
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+	"	movi	%[newval], 0\n"			\
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 	"3:\n"						\
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 	"	.section .fixup,\"ax\"\n"		\
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 	"	.align 4\n"				\
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-	"4:	.long	3b\n"				\
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-	"5:	l32r	%0, 4b\n"			\
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-	"	movi	%1, %3\n"			\
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-	"	jx	%0\n"				\
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+	"	.literal_position\n"			\
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+	"5:	movi	%[oldval], 3b\n"		\
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+	"	movi	%[newval], %[fault]\n"		\
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+	"	jx	%[oldval]\n"			\
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 	"	.previous\n"				\
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 	"	.section __ex_table,\"a\"\n"		\
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-	"	.long 1b,5b,2b,5b\n"			\
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+	"	.long 1b, 5b, 2b, 5b\n"			\
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 	"	.previous\n"				\
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-	: "=&r" (oldval), "=&r" (ret)			\
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-	: "r" (uaddr), "I" (-EFAULT), "r" (oparg)	\
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+	: [oldval] "=&r" (old), [newval] "=&r" (ret)	\
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+	: [addr] "r" (uaddr), [oparg] "r" (arg),	\
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+	  [fault] "I" (-EFAULT)				\
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 	: "memory")
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+#elif XCHAL_HAVE_S32C1I
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+#define __futex_atomic_op(insn, ret, old, uaddr, arg)	\
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+	__asm__ __volatile(				\
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+	"1:	l32i	%[oldval], %[mem]\n"		\
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+		insn "\n"				\
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+	"	wsr	%[oldval], scompare1\n"		\
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+	"2:	s32c1i	%[newval], %[mem]\n"		\
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+	"	bne	%[newval], %[oldval], 1b\n"	\
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+	"	movi	%[newval], 0\n"			\
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+	"3:\n"						\
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+	"	.section .fixup,\"ax\"\n"		\
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+	"	.align 4\n"				\
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+	"	.literal_position\n"			\
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+	"5:	movi	%[oldval], 3b\n"		\
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+	"	movi	%[newval], %[fault]\n"		\
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+	"	jx	%[oldval]\n"			\
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+	"	.previous\n"				\
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+	"	.section __ex_table,\"a\"\n"		\
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+	"	.long 1b, 5b, 2b, 5b\n"			\
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+	"	.previous\n"				\
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+	: [oldval] "=&r" (old), [newval] "=&r" (ret),	\
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+	  [mem] "+m" (*(uaddr))				\
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+	: [oparg] "r" (arg), [fault] "I" (-EFAULT)	\
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+	: "memory")
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+#endif
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68
 
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 static inline int arch_futex_atomic_op_inuser(int op, int oparg, int *oval,
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 		u32 __user *uaddr)
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 {
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+#if XCHAL_HAVE_S32C1I || XCHAL_HAVE_EXCLUSIVE
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 	int oldval = 0, ret;
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-#if !XCHAL_HAVE_S32C1I
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-	return -ENOSYS;
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-#endif
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-
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-	pagefault_disable();
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+	if (!access_ok(uaddr, sizeof(u32)))
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+		return -EFAULT;
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 	switch (op) {
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 	case FUTEX_OP_SET:
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-		__futex_atomic_op("mov %1, %4", ret, oldval, uaddr, oparg);
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+		__futex_atomic_op("mov %[newval], %[oparg]",
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+				  ret, oldval, uaddr, oparg);
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 		break;
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 	case FUTEX_OP_ADD:
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-		__futex_atomic_op("add %1, %0, %4", ret, oldval, uaddr,
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-				oparg);
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+		__futex_atomic_op("add %[newval], %[oldval], %[oparg]",
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+				  ret, oldval, uaddr, oparg);
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 		break;
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 	case FUTEX_OP_OR:
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-		__futex_atomic_op("or %1, %0, %4", ret, oldval, uaddr,
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-				oparg);
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+		__futex_atomic_op("or %[newval], %[oldval], %[oparg]",
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+				  ret, oldval, uaddr, oparg);
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 		break;
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 	case FUTEX_OP_ANDN:
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-		__futex_atomic_op("and %1, %0, %4", ret, oldval, uaddr,
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-				~oparg);
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+		__futex_atomic_op("and %[newval], %[oldval], %[oparg]",
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+				  ret, oldval, uaddr, ~oparg);
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 		break;
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 	case FUTEX_OP_XOR:
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-		__futex_atomic_op("xor %1, %0, %4", ret, oldval, uaddr,
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-				oparg);
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+		__futex_atomic_op("xor %[newval], %[oldval], %[oparg]",
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+				  ret, oldval, uaddr, oparg);
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 		break;
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 	default:
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 		ret = -ENOSYS;
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 	}
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-	pagefault_enable();
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-
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 	if (!ret)
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 		*oval = oldval;
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 	return ret;
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+#else
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+	return -ENOSYS;
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+#endif
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 }
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 static inline int
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 futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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 			      u32 oldval, u32 newval)
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 {
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+#if XCHAL_HAVE_S32C1I || XCHAL_HAVE_EXCLUSIVE
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+	unsigned long tmp;
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 	int ret = 0;
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-	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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+	if (!access_ok(uaddr, sizeof(u32)))
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 		return -EFAULT;
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-
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-#if !XCHAL_HAVE_S32C1I
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-	return -ENOSYS;
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-#endif
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 	__asm__ __volatile__ (
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 	"	# futex_atomic_cmpxchg_inatomic\n"
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-	"	wsr	%5, scompare1\n"
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-	"1:	s32c1i	%1, %4, 0\n"
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-	"	s32i	%1, %6, 0\n"
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+#if XCHAL_HAVE_EXCLUSIVE
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+	"1:	l32ex	%[tmp], %[addr]\n"
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+	"	s32i	%[tmp], %[uval], 0\n"
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+	"	bne	%[tmp], %[oldval], 2f\n"
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+	"	mov	%[tmp], %[newval]\n"
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+	"3:	s32ex	%[tmp], %[addr]\n"
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+	"	getex	%[tmp]\n"
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+	"	beqz	%[tmp], 1b\n"
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+#elif XCHAL_HAVE_S32C1I
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+	"	wsr	%[oldval], scompare1\n"
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+	"1:	s32c1i	%[newval], %[addr], 0\n"
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+	"	s32i	%[newval], %[uval], 0\n"
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+#endif
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 	"2:\n"
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 	"	.section .fixup,\"ax\"\n"
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 	"	.align 4\n"
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-	"3:	.long	2b\n"
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-	"4:	l32r	%1, 3b\n"
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-	"	movi	%0, %7\n"
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-	"	jx	%1\n"
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+	"	.literal_position\n"
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+	"4:	movi	%[tmp], 2b\n"
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+	"	movi	%[ret], %[fault]\n"
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+	"	jx	%[tmp]\n"
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 	"	.previous\n"
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 	"	.section __ex_table,\"a\"\n"
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-	"	.long 1b,4b\n"
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+	"	.long 1b, 4b\n"
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+#if XCHAL_HAVE_EXCLUSIVE
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+	"	.long 3b, 4b\n"
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+#endif
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 	"	.previous\n"
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-	: "+r" (ret), "+r" (newval), "+m" (*uaddr), "+m" (*uval)
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-	: "r" (uaddr), "r" (oldval), "r" (uval), "I" (-EFAULT)
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+	: [ret] "+r" (ret), [newval] "+r" (newval), [tmp] "=&r" (tmp)
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+	: [addr] "r" (uaddr), [oldval] "r" (oldval), [uval] "r" (uval),
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+	  [fault] "I" (-EFAULT)
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 	: "memory");
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 	return ret;
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+#else
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+	return -ENOSYS;
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+#endif
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 }
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-#endif /* __KERNEL__ */
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 #endif /* _ASM_XTENSA_FUTEX_H */