update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/x86/mm/init.c
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@@ -7,8 +7,10 @@
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 #include <linux/swapops.h>
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 #include <linux/kmemleak.h>
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 #include <linux/sched/task.h>
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+#include <linux/sched/mm.h>
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 #include <asm/set_memory.h>
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+#include <asm/cpu_device_id.h>
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 #include <asm/e820/api.h>
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 #include <asm/init.h>
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 #include <asm/page.h>
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@@ -26,6 +28,7 @@
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 #include <asm/pti.h>
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 #include <asm/text-patching.h>
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 #include <asm/memtype.h>
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+#include <asm/paravirt.h>
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 /*
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  * We need to define the tracepoints somewhere, and tlb.c
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@@ -260,6 +263,24 @@
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 	}
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 }
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+#define INTEL_MATCH(_model) { .vendor  = X86_VENDOR_INTEL,	\
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+			      .family  = 6,			\
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+			      .model = _model,			\
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+			    }
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+/*
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+ * INVLPG may not properly flush Global entries
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+ * on these CPUs when PCIDs are enabled.
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+ */
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+static const struct x86_cpu_id invlpg_miss_ids[] = {
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+	INTEL_MATCH(INTEL_FAM6_ALDERLAKE   ),
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+	INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ),
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+	INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ),
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+	INTEL_MATCH(INTEL_FAM6_RAPTORLAKE  ),
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+	INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P),
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+	INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S),
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+	{}
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+};
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+
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 static void setup_pcid(void)
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 {
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 	if (!IS_ENABLED(CONFIG_X86_64))
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@@ -267,6 +288,12 @@
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 	if (!boot_cpu_has(X86_FEATURE_PCID))
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 		return;
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+
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+	if (x86_match_cpu(invlpg_miss_ids)) {
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+		pr_info("Incomplete global flushes, disabling PCID");
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+		setup_clear_cpu_cap(X86_FEATURE_PCID);
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+		return;
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+	}
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 	if (boot_cpu_has(X86_FEATURE_PGE)) {
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 		/*
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@@ -785,9 +812,12 @@
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 	spinlock_t *ptl;
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 	pte_t *ptep;
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-	poking_mm = copy_init_mm();
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+	poking_mm = mm_alloc();
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 	BUG_ON(!poking_mm);
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+	/* Xen PV guests need the PGD to be pinned. */
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+	paravirt_arch_dup_mmap(NULL, poking_mm);
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+
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 	/*
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 	 * Randomize the poking address, but make sure that the following page
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 	 * will be mapped at the same PMD. We need 2 pages, so find space for 3,