.. | .. |
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79 | 79 | */ |
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80 | 80 | flags->bm_control = 0; |
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81 | 81 | } |
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| 82 | + if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) { |
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| 83 | + /* |
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| 84 | + * For all AMD Zen or newer CPUs that support C3, caches |
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| 85 | + * should not be flushed by software while entering C3 |
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| 86 | + * type state. Set bm->check to 1 so that kernel doesn't |
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| 87 | + * need to execute cache flush operation. |
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| 88 | + */ |
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| 89 | + flags->bm_check = 1; |
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| 90 | + /* |
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| 91 | + * In current AMD C state implementation ARB_DIS is no longer |
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| 92 | + * used. So set bm_control to zero to indicate ARB_DIS is not |
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| 93 | + * required while entering C3 type state. |
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| 94 | + */ |
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| 95 | + flags->bm_control = 0; |
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| 96 | + } |
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82 | 97 | } |
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83 | 98 | EXPORT_SYMBOL(acpi_processor_power_init_bm_check); |
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84 | 99 | |
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