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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/arch/x86/entry/calling.h
....@@ -6,6 +6,8 @@
66 #include <asm/percpu.h>
77 #include <asm/asm-offsets.h>
88 #include <asm/processor-flags.h>
9
+#include <asm/msr.h>
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+#include <asm/nospec-branch.h>
911 
1012 /*
1113 
....@@ -146,27 +148,19 @@
146148 
147149 .endm
148150 
149
-.macro POP_REGS pop_rdi=1 skip_r11rcx=0
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+.macro POP_REGS pop_rdi=1
150152 	popq %r15
151153 	popq %r14
152154 	popq %r13
153155 	popq %r12
154156 	popq %rbp
155157 	popq %rbx
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-	.if \skip_r11rcx
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-	popq %rsi
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-	.else
159158 	popq %r11
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-	.endif
161159 	popq %r10
162160 	popq %r9
163161 	popq %r8
164162 	popq %rax
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-	.if \skip_r11rcx
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-	popq %rsi
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-	.else
168163 	popq %rcx
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-	.endif
170164 	popq %rdx
171165 	popq %rsi
172166 	.if \pop_rdi
....@@ -317,6 +311,66 @@
317311 #endif
318312 
319313 /*
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+ * IBRS kernel mitigation for Spectre_v2.
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+ *
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+ * Assumes full context is established (PUSH_REGS, CR3 and GS) and it clobbers
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+ * the regs it uses (AX, CX, DX). Must be called before the first RET
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+ * instruction (NOTE! UNTRAIN_RET includes a RET instruction)
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+ *
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+ * The optional argument is used to save/restore the current value,
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+ * which is used on the paranoid paths.
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+ *
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+ * Assumes x86_spec_ctrl_{base,current} to have SPEC_CTRL_IBRS set.
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+ */
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+.macro IBRS_ENTER save_reg
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+#ifdef CONFIG_CPU_IBRS_ENTRY
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+	ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
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+	movl	$MSR_IA32_SPEC_CTRL, %ecx
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+
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+.ifnb \save_reg
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+	rdmsr
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+	shl	$32, %rdx
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+	or	%rdx, %rax
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+	mov	%rax, \save_reg
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+	test	$SPEC_CTRL_IBRS, %eax
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+	jz	.Ldo_wrmsr_\@
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+	lfence
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+	jmp	.Lend_\@
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+.Ldo_wrmsr_\@:
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+.endif
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+
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+	movq	PER_CPU_VAR(x86_spec_ctrl_current), %rdx
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+	movl	%edx, %eax
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+	shr	$32, %rdx
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+	wrmsr
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+.Lend_\@:
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+#endif
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+.endm
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+
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+/*
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+ * Similar to IBRS_ENTER, requires KERNEL GS,CR3 and clobbers (AX, CX, DX)
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+ * regs. Must be called after the last RET.
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+ */
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+.macro IBRS_EXIT save_reg
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+#ifdef CONFIG_CPU_IBRS_ENTRY
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+	ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
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+	movl	$MSR_IA32_SPEC_CTRL, %ecx
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+
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+.ifnb \save_reg
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+	mov	\save_reg, %rdx
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+.else
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+	movq	PER_CPU_VAR(x86_spec_ctrl_current), %rdx
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+	andl	$(~SPEC_CTRL_IBRS), %edx
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+.endif
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+
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+	movl	%edx, %eax
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+	shr	$32, %rdx
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+	wrmsr
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+.Lend_\@:
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+#endif
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+.endm
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+
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+/*
320374  * Mitigate Spectre v1 for conditional swapgs code paths.
321375  *
322376  * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
....@@ -333,18 +387,66 @@
333387 	ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
334388 .endm
335389 
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-#endif /* CONFIG_X86_64 */
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-
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-/*
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- * This does 'call enter_from_user_mode' unless we can avoid it based on
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- * kernel config or using the static jump infrastructure.
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- */
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-.macro CALL_enter_from_user_mode
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-#ifdef CONFIG_CONTEXT_TRACKING
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-#ifdef CONFIG_JUMP_LABEL
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-	STATIC_JUMP_IF_FALSE .Lafter_call_\@, context_tracking_enabled, def=0
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-#endif
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-	call enter_from_user_mode
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-.Lafter_call_\@:
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+.macro STACKLEAK_ERASE_NOCLOBBER
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+#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
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+	PUSH_AND_CLEAR_REGS
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+	call stackleak_erase
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+	POP_REGS
349395 #endif
350396 .endm
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+
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+.macro SAVE_AND_SET_GSBASE scratch_reg:req save_reg:req
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+	rdgsbase \save_reg
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+	GET_PERCPU_BASE \scratch_reg
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+	wrgsbase \scratch_reg
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+.endm
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+
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+#else /* CONFIG_X86_64 */
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+# undef		UNWIND_HINT_IRET_REGS
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+# define	UNWIND_HINT_IRET_REGS
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+#endif /* !CONFIG_X86_64 */
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+
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+.macro STACKLEAK_ERASE
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+#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
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+	call stackleak_erase
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+#endif
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+.endm
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+
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+#ifdef CONFIG_SMP
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+
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+/*
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+ * CPU/node NR is loaded from the limit (size) field of a special segment
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+ * descriptor entry in GDT.
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+ */
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+.macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req
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+	movq	$__CPUNODE_SEG, \reg
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+#ifdef __clang__
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+	.long 0xc0030f48
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+#else
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+	lsl	\reg, \reg
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+#endif
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+.endm
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+
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+/*
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+ * Fetch the per-CPU GSBASE value for this processor and put it in @reg.
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+ * We normally use %gs for accessing per-CPU data, but we are setting up
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+ * %gs here and obviously can not use %gs itself to access per-CPU data.
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+ *
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+ * Do not use RDPID, because KVM loads guest's TSC_AUX on vm-entry and
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+ * may not restore the host's value until the CPU returns to userspace.
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+ * Thus the kernel would consume a guest's TSC_AUX if an NMI arrives
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+ * while running KVM's run loop.
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+ */
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+.macro GET_PERCPU_BASE reg:req
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+	LOAD_CPU_AND_NODE_SEG_LIMIT \reg
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+	andq	$VDSO_CPUNODE_MASK, \reg
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+	movq	__per_cpu_offset(, \reg, 8), \reg
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+.endm
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+
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+#else
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+
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+.macro GET_PERCPU_BASE reg:req
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+	movq	pcpu_unit_offsets(%rip), \reg
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+.endm
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+
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+#endif /* CONFIG_SMP */