update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/x86/boot/compressed/head_64.S
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@@ -454,11 +454,25 @@
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 	/* Save the trampoline address in RCX */
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 	movq	%rax, %rcx
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+	/* Set up 32-bit addressable stack */
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+	leaq	TRAMPOLINE_32BIT_STACK_END(%rcx), %rsp
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+
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 	/*
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-	 * Load the address of trampoline_return() into RDI.
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-	 * It will be used by the trampoline to return to the main code.
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+	 * Preserve live 64-bit registers on the stack: this is necessary
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+	 * because the architecture does not guarantee that GPRs will retain
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+	 * their full 64-bit values across a 32-bit mode switch.
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+	 */
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+	pushq	%rbp
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+	pushq	%rbx
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+	pushq	%rsi
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+
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+	/*
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+	 * Push the 64-bit address of trampoline_return() onto the new stack.
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+	 * It will be used by the trampoline to return to the main code. Due to
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+	 * the 32-bit mode switch, it cannot be kept it in a register either.
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 	 */
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 	leaq	trampoline_return(%rip), %rdi
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+	pushq	%rdi
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 	/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
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 	pushq	$__KERNEL32_CS
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@@ -466,6 +480,11 @@
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 	pushq	%rax
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 	lretq
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 trampoline_return:
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+	/* Restore live 64-bit registers */
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+	popq	%rsi
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+	popq	%rbx
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+	popq	%rbp
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+
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 	/* Restore the stack, the 32-bit trampoline uses its own stack */
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 	leaq	rva(boot_stack_end)(%rbx), %rsp
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@@ -586,7 +605,7 @@
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 /*
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  * This is the 32-bit trampoline that will be copied over to low memory.
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  *
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- * RDI contains the return address (might be above 4G).
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+ * Return address is at the top of the stack (might be above 4G).
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  * ECX contains the base address of the trampoline memory.
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  * Non zero RDX means trampoline needs to enable 5-level paging.
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  */
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@@ -595,9 +614,6 @@
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 	movl	$__KERNEL_DS, %eax
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 	movl	%eax, %ds
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 	movl	%eax, %ss
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-
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-	/* Set up new stack */
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-	leal	TRAMPOLINE_32BIT_STACK_END(%ecx), %esp
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 	/* Disable paging */
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 	movl	%cr0, %eax
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@@ -658,7 +674,7 @@
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 	.code64
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 SYM_FUNC_START_LOCAL_NOALIGN(.Lpaging_enabled)
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 	/* Return from the trampoline */
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-	jmp	*%rdi
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+	retq
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 SYM_FUNC_END(.Lpaging_enabled)
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 	/*