update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/sh/drivers/dma/dma-sh.c
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@@ -19,6 +19,18 @@
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 #include <cpu/dma.h>
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 /*
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+ * Some of the SoCs feature two DMAC modules. In such a case, the channels are
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+ * distributed equally among them.
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+ */
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+#ifdef	SH_DMAC_BASE1
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+#define	SH_DMAC_NR_MD_CH	(CONFIG_NR_ONCHIP_DMA_CHANNELS / 2)
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+#else
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+#define	SH_DMAC_NR_MD_CH	CONFIG_NR_ONCHIP_DMA_CHANNELS
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+#endif
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+
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+#define	SH_DMAC_CH_SZ		0x10
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+
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+/*
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  * Define the default configuration for dual address memory-memory transfer.
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  * The 0x400 value represents auto-request, external->external.
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  */
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@@ -29,7 +41,7 @@
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 	unsigned long base = SH_DMAC_BASE0;
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 #ifdef SH_DMAC_BASE1
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-	if (chan >= 6)
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+	if (chan >= SH_DMAC_NR_MD_CH)
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 		base = SH_DMAC_BASE1;
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 #endif
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@@ -40,13 +52,13 @@
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 {
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 	unsigned long base = dma_find_base(chan);
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-	/* Normalize offset calculation */
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-	if (chan >= 9)
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-		chan -= 6;
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-	if (chan >= 4)
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-		base += 0x10;
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+	chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ;
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-	return base + (chan * 0x10);
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+	/* DMAOR is placed inside the channel register space. Step over it. */
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+	if (chan >= DMAOR)
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+		base += SH_DMAC_CH_SZ;
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+
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+	return base + chan;
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 }
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 #ifdef CONFIG_SH_DMA_IRQ_MULTI
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@@ -250,12 +262,11 @@
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 #define NR_DMAOR	1
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 #endif
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-/*
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- * DMAOR bases are broken out amongst channel groups. DMAOR0 manages
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- * channels 0 - 5, DMAOR1 6 - 11 (optional).
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- */
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-#define dmaor_read_reg(n)		__raw_readw(dma_find_base((n)*6))
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-#define dmaor_write_reg(n, data)	__raw_writew(data, dma_find_base(n)*6)
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+#define dmaor_read_reg(n)		__raw_readw(dma_find_base((n) * \
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+						    SH_DMAC_NR_MD_CH) + DMAOR)
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+#define dmaor_write_reg(n, data)	__raw_writew(data, \
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+						     dma_find_base((n) * \
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+						     SH_DMAC_NR_MD_CH) + DMAOR)
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 static inline int dmaor_reset(int no)
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 {