update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/powerpc/platforms/powernv/pci.h
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@@ -2,14 +2,12 @@
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 #ifndef __POWERNV_PCI_H
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 #define __POWERNV_PCI_H
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+#include <linux/compiler.h>		/* for __printf */
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 #include <linux/iommu.h>
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 #include <asm/iommu.h>
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 #include <asm/msi_bitmap.h>
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9
 
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 struct pci_dn;
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-
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-/* Maximum possible number of ATSD MMIO registers per NPU */
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-#define NV_NMMU_ATSD_REGS 8
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 enum pnv_phb_type {
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 	PNV_PHB_IODA1		= 0,
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@@ -34,6 +32,24 @@
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 #define PNV_IODA_PE_MASTER	(1 << 3)	/* Master PE in compound case	*/
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 #define PNV_IODA_PE_SLAVE	(1 << 4)	/* Slave PE in compound case	*/
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 #define PNV_IODA_PE_VF		(1 << 5)	/* PE for one VF 		*/
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+
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+/*
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+ * A brief note on PNV_IODA_PE_BUS_ALL
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+ *
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+ * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses
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+ * the Requester ID field of the PCIe request header to determine the device
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+ * (and PE) that initiated a DMA. In legacy PCI individual memory read/write
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+ * requests aren't tagged with the RID. To work around this the PCIe-to-PCI
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+ * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side.
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+ *
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+ * PCIe-to-X bridges have a similar issue even though PCI-X requests also have
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+ * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take
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+ * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe
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+ * side of the bridge.
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+ *
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+ * To work around these problems we use the BUS_ALL flag since every subordinate
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+ * bus of the bridge should go into the same PE.
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+ */
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 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
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 #define PNV_IODA_STOPPED_STATE	0x8000000000000000
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@@ -65,12 +81,20 @@
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 	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
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 	struct iommu_table_group table_group;
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+	struct npu_comp		*npucomp;
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85
 
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 	/* 64-bit TCE bypass region */
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 	bool			tce_bypass_enabled;
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 	uint64_t		tce_bypass_base;
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-	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
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+	/*
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+	 * Used to track whether we've done DMA setup for this PE or not. We
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+	 * want to defer allocating TCE tables, etc until we've added a
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+	 * non-bridge device to the PE.
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+	 */
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+	bool			dma_setup_done;
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+
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+	/* MSIs. MVE index is identical for 32 and 64 bit MSI
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 	 * and -1 if not supported. (It's actually identical to the
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 	 * PE number)
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 	 */
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@@ -79,9 +103,6 @@
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 	/* PEs in compound case */
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 	struct pnv_ioda_pe	*master;
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 	struct list_head	slaves;
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-
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-	/* PCI peer-to-peer*/
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-	int			p2p_initiator_count;
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 	/* Link in list of PE#s */
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 	struct list_head	list;
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@@ -106,20 +127,13 @@
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 	struct dentry		*dbgfs;
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 #endif
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129
 
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-#ifdef CONFIG_PCI_MSI
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 	unsigned int		msi_base;
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 	unsigned int		msi32_support;
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 	struct msi_bitmap	msi_bmp;
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-#endif
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 	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
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 			 unsigned int hwirq, unsigned int virq,
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 			 unsigned int is_64, struct msi_msg *msg);
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-	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
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-	void (*fixup_phb)(struct pci_controller *hose);
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 	int (*init_m64)(struct pnv_phb *phb);
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-	void (*reserve_m64_pe)(struct pci_bus *bus,
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-			       unsigned long *pe_bitmap, bool all);
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-	struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
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 	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
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 	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
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 	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
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@@ -129,7 +143,6 @@
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 		unsigned int		total_pe_num;
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 		unsigned int		reserved_pe_idx;
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 		unsigned int		root_pe_idx;
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-		bool			root_pe_populated;
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 		/* 32-bit MMIO window */
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 		unsigned int		m32_size;
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@@ -141,6 +154,7 @@
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 		unsigned long		m64_size;
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 		unsigned long		m64_segsize;
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 		unsigned long		m64_base;
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+#define MAX_M64_BARS 64
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 		unsigned long		m64_bar_alloc;
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 		/* IO ports */
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@@ -179,22 +193,90 @@
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 	/* PHB and hub diagnostics */
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 	unsigned int		diag_data_size;
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 	u8			*diag_data;
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-
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-	/* Nvlink2 data */
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-	struct npu {
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-		int index;
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-		__be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
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-		unsigned int mmio_atsd_count;
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-
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-		/* Bitmask for MMIO register usage */
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-		unsigned long mmio_atsd_usage;
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-
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-		/* Do we need to explicitly flush the nest mmu? */
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-		bool nmmu_flush;
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-	} npu;
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-
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-	int p2p_target_count;
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 };
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+
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+
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+/* IODA PE management */
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+
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+static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
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+{
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+	/*
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+	 * WARNING: We cannot rely on the resource flags. The Linux PCI
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+	 * allocation code sometimes decides to put a 64-bit prefetchable
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+	 * BAR in the 32-bit window, so we have to compare the addresses.
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+	 *
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+	 * For simplicity we only test resource start.
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+	 */
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+	return (r->start >= phb->ioda.m64_base &&
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+		r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
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+}
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+
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+static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
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+{
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+	unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
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+
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+	return (resource_flags & flags) == flags;
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+}
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+
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+int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
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+int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
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+
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+void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
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+void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe);
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+
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+struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count);
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+void pnv_ioda_free_pe(struct pnv_ioda_pe *pe);
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+
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+#ifdef CONFIG_PCI_IOV
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+/*
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+ * For SR-IOV we want to put each VF's MMIO resource in to a separate PE.
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+ * This requires a bit of acrobatics with the MMIO -> PE configuration
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+ * and this structure is used to keep track of it all.
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+ */
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+struct pnv_iov_data {
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+	/* number of VFs enabled */
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+	u16     num_vfs;
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+
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+	/* pointer to the array of VF PEs. num_vfs long*/
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+	struct pnv_ioda_pe *vf_pe_arr;
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+
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+	/* Did we map the VF BAR with single-PE IODA BARs? */
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+	bool    m64_single_mode[PCI_SRIOV_NUM_BARS];
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+
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+	/*
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+	 * True if we're using any segmented windows. In that case we need
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+	 * shift the start of the IOV resource the segment corresponding to
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+	 * the allocated PE.
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+	 */
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+	bool    need_shift;
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+
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+	/*
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+	 * Bit mask used to track which m64 windows are used to map the
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+	 * SR-IOV BARs for this device.
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+	 */
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+	DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS);
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+
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+	/*
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+	 * If we map the SR-IOV BARs with a segmented window then
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+	 * parts of that window will be "claimed" by other PEs.
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+	 *
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+	 * "holes" here is used to reserve the leading portion
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+	 * of the window that is used by other (non VF) PEs.
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+	 */
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+	struct resource holes[PCI_SRIOV_NUM_BARS];
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+};
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+
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+static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev)
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+{
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+	return pdev->dev.archdata.iov_data;
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+}
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+
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+void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev);
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+resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno);
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+
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+int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
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+int pnv_pcibios_sriov_disable(struct pci_dev *pdev);
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+#endif /* CONFIG_PCI_IOV */
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 extern struct pci_ops pnv_pci_ops;
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@@ -210,18 +292,20 @@
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 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
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 extern void pnv_pci_init_npu_phb(struct device_node *np);
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 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
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+extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr);
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 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
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 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
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-extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
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-extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
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 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
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 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
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+extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn);
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 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
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 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
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-extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
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+extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
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+		__u64 window_size, __u32 levels);
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 extern int pnv_eeh_post_init(void);
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+__printf(3, 4)
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 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
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 			    const char *fmt, ...);
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 #define pe_err(pe, fmt, ...)					\
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@@ -234,13 +318,7 @@
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 /* Nvlink functions */
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 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
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 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
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-extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
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-extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
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-		struct iommu_table *tbl);
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-extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
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-extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
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-extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
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-extern int pnv_npu2_init(struct pnv_phb *phb);
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+extern void pnv_pci_npu_setup_iommu_groups(void);
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 /* pci-ioda-tce.c */
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 #define POWERNV_IOMMU_DEFAULT_LEVELS	2
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@@ -271,4 +349,16 @@
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 		void *tce_mem, u64 tce_size,
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 		u64 dma_offset, unsigned int page_shift);
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+extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
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+
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+static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus)
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+{
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+	struct pci_controller *hose = bus->sysdata;
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+
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+	if (hose)
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+		return hose->private_data;
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+
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+	return NULL;
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+}
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+
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 #endif /* __POWERNV_PCI_H */