update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/powerpc/perf/power5+-pmu.c
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@@ -1,18 +1,16 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Performance counter support for POWER5+/++ (not POWER5) processors.
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  *
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  * Copyright 2009 Paul Mackerras, IBM Corporation.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or (at your option) any later version.
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  */
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 #include <linux/kernel.h>
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 #include <linux/perf_event.h>
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 #include <linux/string.h>
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 #include <asm/reg.h>
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 #include <asm/cputable.h>
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+
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+#include "internal.h"
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 /*
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  * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3)
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@@ -452,7 +450,8 @@
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 }
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 static int power5p_compute_mmcr(u64 event[], int n_ev,
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-				unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
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+				unsigned int hwc[], struct mmcr_regs *mmcr,
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+				struct perf_event *pevents[])
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 {
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 	unsigned long mmcr1 = 0;
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 	unsigned long mmcra = 0;
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@@ -590,20 +589,20 @@
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 	}
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 	/* Return MMCRx values */
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-	mmcr[0] = 0;
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+	mmcr->mmcr0 = 0;
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 	if (pmc_inuse & 1)
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-		mmcr[0] = MMCR0_PMC1CE;
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+		mmcr->mmcr0 = MMCR0_PMC1CE;
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 	if (pmc_inuse & 0x3e)
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-		mmcr[0] |= MMCR0_PMCjCE;
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-	mmcr[1] = mmcr1;
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-	mmcr[2] = mmcra;
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+		mmcr->mmcr0 |= MMCR0_PMCjCE;
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+	mmcr->mmcr1 = mmcr1;
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+	mmcr->mmcra = mmcra;
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 	return 0;
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 }
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-static void power5p_disable_pmc(unsigned int pmc, unsigned long mmcr[])
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+static void power5p_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
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 {
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 	if (pmc <= 3)
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-		mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
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+		mmcr->mmcr1 &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
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 }
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 static int power5p_generic_events[] = {
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@@ -622,7 +621,7 @@
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  * 0 means not supported, -1 means nonsensical, other values
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  * are event codes.
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  */
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-static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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+static u64 power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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 	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
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 		[C(OP_READ)] = {	0x1c10a8,	0x3c1088	},
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 		[C(OP_WRITE)] = {	0x2c10a8,	0xc10c3		},
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@@ -677,7 +676,7 @@
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 	.cache_events		= &power5p_cache_events,
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 };
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-static int __init init_power5p_pmu(void)
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+int init_power5p_pmu(void)
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 {
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 	if (!cur_cpu_spec->oprofile_cpu_type ||
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 	    (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5+")
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@@ -686,5 +685,3 @@
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 	return register_power_pmu(&power5p_pmu);
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 }
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-
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-early_initcall(init_power5p_pmu);