update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/mips/kernel/unaligned.c
..
..
@@ -89,10 +89,9 @@
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 #include <asm/fpu.h>
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 #include <asm/fpu_emulator.h>
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 #include <asm/inst.h>
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+#include <asm/unaligned-emul.h>
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+#include <asm/mmu_context.h>
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 #include <linux/uaccess.h>
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-
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-#define STR(x)	__STR(x)
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-#define __STR(x)  #x
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 enum {
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 	UNALIGNED_ACTION_QUIET,
..
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@@ -107,794 +106,15 @@
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 #endif
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 extern void show_registers(struct pt_regs *regs);
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-#ifdef __BIG_ENDIAN
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-#define     _LoadHW(addr, value, res, type)  \
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-do {                                                        \
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-		__asm__ __volatile__ (".set\tnoat\n"        \
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-			"1:\t"type##_lb("%0", "0(%2)")"\n"  \
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-			"2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
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-			"sll\t%0, 0x8\n\t"                  \
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-			"or\t%0, $1\n\t"                    \
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-			"li\t%1, 0\n"                       \
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-			"3:\t.set\tat\n\t"                  \
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-			".insn\n\t"                         \
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-			".section\t.fixup,\"ax\"\n\t"       \
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-			"4:\tli\t%1, %3\n\t"                \
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-			"j\t3b\n\t"                         \
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-			".previous\n\t"                     \
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-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 4b\n\t"              \
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-			STR(PTR)"\t2b, 4b\n\t"              \
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-			".previous"                         \
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-			: "=&r" (value), "=r" (res)         \
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-			: "r" (addr), "i" (-EFAULT));       \
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-} while(0)
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-
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-#ifndef CONFIG_CPU_MIPSR6
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-#define     _LoadW(addr, value, res, type)   \
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-do {                                                        \
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-		__asm__ __volatile__ (                      \
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-			"1:\t"type##_lwl("%0", "(%2)")"\n"   \
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-			"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
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-			"li\t%1, 0\n"                       \
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-			"3:\n\t"                            \
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-			".insn\n\t"                         \
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-			".section\t.fixup,\"ax\"\n\t"       \
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-			"4:\tli\t%1, %3\n\t"                \
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-			"j\t3b\n\t"                         \
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-			".previous\n\t"                     \
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-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 4b\n\t"              \
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-			STR(PTR)"\t2b, 4b\n\t"              \
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-			".previous"                         \
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-			: "=&r" (value), "=r" (res)         \
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-			: "r" (addr), "i" (-EFAULT));       \
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-} while(0)
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-
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-#else
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-/* MIPSR6 has no lwl instruction */
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-#define     _LoadW(addr, value, res, type) \
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-do {                                                        \
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-		__asm__ __volatile__ (			    \
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-			".set\tpush\n"			    \
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-			".set\tnoat\n\t"		    \
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-			"1:"type##_lb("%0", "0(%2)")"\n\t"  \
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-			"2:"type##_lbu("$1", "1(%2)")"\n\t" \
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-			"sll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"3:"type##_lbu("$1", "2(%2)")"\n\t" \
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-			"sll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"4:"type##_lbu("$1", "3(%2)")"\n\t" \
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-			"sll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"li\t%1, 0\n"			    \
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-			".set\tpop\n"			    \
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-			"10:\n\t"			    \
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-			".insn\n\t"			    \
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-			".section\t.fixup,\"ax\"\n\t"	    \
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-			"11:\tli\t%1, %3\n\t"		    \
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-			"j\t10b\n\t"			    \
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-			".previous\n\t"			    \
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-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 11b\n\t"		    \
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-			STR(PTR)"\t2b, 11b\n\t"		    \
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-			STR(PTR)"\t3b, 11b\n\t"		    \
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-			STR(PTR)"\t4b, 11b\n\t"		    \
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-			".previous"			    \
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-			: "=&r" (value), "=r" (res)	    \
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-			: "r" (addr), "i" (-EFAULT));       \
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-} while(0)
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-
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-#endif /* CONFIG_CPU_MIPSR6 */
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-
191
-#define     _LoadHWU(addr, value, res, type) \
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-do {                                                        \
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-		__asm__ __volatile__ (                      \
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-			".set\tnoat\n"                      \
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-			"1:\t"type##_lbu("%0", "0(%2)")"\n" \
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-			"2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
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-			"sll\t%0, 0x8\n\t"                  \
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-			"or\t%0, $1\n\t"                    \
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-			"li\t%1, 0\n"                       \
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-			"3:\n\t"                            \
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-			".insn\n\t"                         \
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-			".set\tat\n\t"                      \
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-			".section\t.fixup,\"ax\"\n\t"       \
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-			"4:\tli\t%1, %3\n\t"                \
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-			"j\t3b\n\t"                         \
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-			".previous\n\t"                     \
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-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 4b\n\t"              \
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-			STR(PTR)"\t2b, 4b\n\t"              \
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-			".previous"                         \
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-			: "=&r" (value), "=r" (res)         \
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-			: "r" (addr), "i" (-EFAULT));       \
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-} while(0)
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-
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-#ifndef CONFIG_CPU_MIPSR6
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-#define     _LoadWU(addr, value, res, type)  \
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-do {                                                        \
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-		__asm__ __volatile__ (                      \
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-			"1:\t"type##_lwl("%0", "(%2)")"\n"  \
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-			"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
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-			"dsll\t%0, %0, 32\n\t"              \
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-			"dsrl\t%0, %0, 32\n\t"              \
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-			"li\t%1, 0\n"                       \
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-			"3:\n\t"                            \
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-			".insn\n\t"                         \
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-			"\t.section\t.fixup,\"ax\"\n\t"     \
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-			"4:\tli\t%1, %3\n\t"                \
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-			"j\t3b\n\t"                         \
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-			".previous\n\t"                     \
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-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 4b\n\t"              \
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-			STR(PTR)"\t2b, 4b\n\t"              \
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-			".previous"                         \
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-			: "=&r" (value), "=r" (res)         \
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-			: "r" (addr), "i" (-EFAULT));       \
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-} while(0)
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-
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-#define     _LoadDW(addr, value, res)  \
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-do {                                                        \
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-		__asm__ __volatile__ (                      \
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-			"1:\tldl\t%0, (%2)\n"               \
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-			"2:\tldr\t%0, 7(%2)\n\t"            \
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-			"li\t%1, 0\n"                       \
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-			"3:\n\t"                            \
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-			".insn\n\t"                         \
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-			"\t.section\t.fixup,\"ax\"\n\t"     \
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-			"4:\tli\t%1, %3\n\t"                \
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-			"j\t3b\n\t"                         \
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-			".previous\n\t"                     \
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-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 4b\n\t"              \
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-			STR(PTR)"\t2b, 4b\n\t"              \
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-			".previous"                         \
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-			: "=&r" (value), "=r" (res)         \
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-			: "r" (addr), "i" (-EFAULT));       \
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-} while(0)
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-
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-#else
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-/* MIPSR6 has not lwl and ldl instructions */
260
-#define	    _LoadWU(addr, value, res, type) \
261
-do {                                                        \
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-		__asm__ __volatile__ (			    \
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-			".set\tpush\n\t"		    \
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-			".set\tnoat\n\t"		    \
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-			"1:"type##_lbu("%0", "0(%2)")"\n\t" \
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-			"2:"type##_lbu("$1", "1(%2)")"\n\t" \
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-			"sll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"3:"type##_lbu("$1", "2(%2)")"\n\t" \
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-			"sll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"4:"type##_lbu("$1", "3(%2)")"\n\t" \
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-			"sll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"li\t%1, 0\n"			    \
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-			".set\tpop\n"			    \
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-			"10:\n\t"			    \
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-			".insn\n\t"			    \
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-			".section\t.fixup,\"ax\"\n\t"	    \
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-			"11:\tli\t%1, %3\n\t"		    \
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-			"j\t10b\n\t"			    \
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-			".previous\n\t"			    \
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-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 11b\n\t"		    \
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-			STR(PTR)"\t2b, 11b\n\t"		    \
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-			STR(PTR)"\t3b, 11b\n\t"		    \
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-			STR(PTR)"\t4b, 11b\n\t"		    \
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-			".previous"			    \
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-			: "=&r" (value), "=r" (res)	    \
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-			: "r" (addr), "i" (-EFAULT));       \
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-} while(0)
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-
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-#define     _LoadDW(addr, value, res)  \
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-do {                                                        \
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-		__asm__ __volatile__ (			    \
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-			".set\tpush\n\t"		    \
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-			".set\tnoat\n\t"		    \
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-			"1:lb\t%0, 0(%2)\n\t"    	    \
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-			"2:lbu\t $1, 1(%2)\n\t"   	    \
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-			"dsll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"3:lbu\t$1, 2(%2)\n\t"   	    \
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-			"dsll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"4:lbu\t$1, 3(%2)\n\t"   	    \
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-			"dsll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"5:lbu\t$1, 4(%2)\n\t"   	    \
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-			"dsll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"6:lbu\t$1, 5(%2)\n\t"   	    \
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-			"dsll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"7:lbu\t$1, 6(%2)\n\t"   	    \
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-			"dsll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"8:lbu\t$1, 7(%2)\n\t"   	    \
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-			"dsll\t%0, 0x8\n\t"		    \
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-			"or\t%0, $1\n\t"		    \
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-			"li\t%1, 0\n"			    \
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-			".set\tpop\n\t"			    \
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-			"10:\n\t"			    \
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-			".insn\n\t"			    \
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-			".section\t.fixup,\"ax\"\n\t"	    \
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-			"11:\tli\t%1, %3\n\t"		    \
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-			"j\t10b\n\t"			    \
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-			".previous\n\t"			    \
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-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 11b\n\t"		    \
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-			STR(PTR)"\t2b, 11b\n\t"		    \
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-			STR(PTR)"\t3b, 11b\n\t"		    \
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-			STR(PTR)"\t4b, 11b\n\t"		    \
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-			STR(PTR)"\t5b, 11b\n\t"		    \
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-			STR(PTR)"\t6b, 11b\n\t"		    \
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-			STR(PTR)"\t7b, 11b\n\t"		    \
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-			STR(PTR)"\t8b, 11b\n\t"		    \
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-			".previous"			    \
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-			: "=&r" (value), "=r" (res)	    \
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-			: "r" (addr), "i" (-EFAULT));       \
340
-} while(0)
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-
342
-#endif /* CONFIG_CPU_MIPSR6 */
343
-
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-
345
-#define     _StoreHW(addr, value, res, type) \
346
-do {                                                        \
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-		__asm__ __volatile__ (                      \
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-			".set\tnoat\n"                      \
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-			"1:\t"type##_sb("%1", "1(%2)")"\n"  \
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-			"srl\t$1, %1, 0x8\n"                \
351
-			"2:\t"type##_sb("$1", "0(%2)")"\n"  \
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-			".set\tat\n\t"                      \
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-			"li\t%0, 0\n"                       \
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-			"3:\n\t"                            \
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-			".insn\n\t"                         \
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-			".section\t.fixup,\"ax\"\n\t"       \
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-			"4:\tli\t%0, %3\n\t"                \
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-			"j\t3b\n\t"                         \
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-			".previous\n\t"                     \
360
-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 4b\n\t"              \
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-			STR(PTR)"\t2b, 4b\n\t"              \
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-			".previous"                         \
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-			: "=r" (res)                        \
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-			: "r" (value), "r" (addr), "i" (-EFAULT));\
366
-} while(0)
367
-
368
-#ifndef CONFIG_CPU_MIPSR6
369
-#define     _StoreW(addr, value, res, type)  \
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-do {                                                        \
371
-		__asm__ __volatile__ (                      \
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-			"1:\t"type##_swl("%1", "(%2)")"\n"  \
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-			"2:\t"type##_swr("%1", "3(%2)")"\n\t"\
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-			"li\t%0, 0\n"                       \
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-			"3:\n\t"                            \
376
-			".insn\n\t"                         \
377
-			".section\t.fixup,\"ax\"\n\t"       \
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-			"4:\tli\t%0, %3\n\t"                \
379
-			"j\t3b\n\t"                         \
380
-			".previous\n\t"                     \
381
-			".section\t__ex_table,\"a\"\n\t"    \
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-			STR(PTR)"\t1b, 4b\n\t"              \
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-			STR(PTR)"\t2b, 4b\n\t"              \
384
-			".previous"                         \
385
-		: "=r" (res)                                \
386
-		: "r" (value), "r" (addr), "i" (-EFAULT));  \
387
-} while(0)
388
-
389
-#define     _StoreDW(addr, value, res) \
390
-do {                                                        \
391
-		__asm__ __volatile__ (                      \
392
-			"1:\tsdl\t%1,(%2)\n"                \
393
-			"2:\tsdr\t%1, 7(%2)\n\t"            \
394
-			"li\t%0, 0\n"                       \
395
-			"3:\n\t"                            \
396
-			".insn\n\t"                         \
397
-			".section\t.fixup,\"ax\"\n\t"       \
398
-			"4:\tli\t%0, %3\n\t"                \
399
-			"j\t3b\n\t"                         \
400
-			".previous\n\t"                     \
401
-			".section\t__ex_table,\"a\"\n\t"    \
402
-			STR(PTR)"\t1b, 4b\n\t"              \
403
-			STR(PTR)"\t2b, 4b\n\t"              \
404
-			".previous"                         \
405
-		: "=r" (res)                                \
406
-		: "r" (value), "r" (addr), "i" (-EFAULT));  \
407
-} while(0)
408
-
409
-#else
410
-/* MIPSR6 has no swl and sdl instructions */
411
-#define     _StoreW(addr, value, res, type)  \
412
-do {                                                        \
413
-		__asm__ __volatile__ (                      \
414
-			".set\tpush\n\t"		    \
415
-			".set\tnoat\n\t"		    \
416
-			"1:"type##_sb("%1", "3(%2)")"\n\t"  \
417
-			"srl\t$1, %1, 0x8\n\t"		    \
418
-			"2:"type##_sb("$1", "2(%2)")"\n\t"  \
419
-			"srl\t$1, $1,  0x8\n\t"		    \
420
-			"3:"type##_sb("$1", "1(%2)")"\n\t"  \
421
-			"srl\t$1, $1, 0x8\n\t"		    \
422
-			"4:"type##_sb("$1", "0(%2)")"\n\t"  \
423
-			".set\tpop\n\t"			    \
424
-			"li\t%0, 0\n"			    \
425
-			"10:\n\t"			    \
426
-			".insn\n\t"			    \
427
-			".section\t.fixup,\"ax\"\n\t"	    \
428
-			"11:\tli\t%0, %3\n\t"		    \
429
-			"j\t10b\n\t"			    \
430
-			".previous\n\t"			    \
431
-			".section\t__ex_table,\"a\"\n\t"    \
432
-			STR(PTR)"\t1b, 11b\n\t"		    \
433
-			STR(PTR)"\t2b, 11b\n\t"		    \
434
-			STR(PTR)"\t3b, 11b\n\t"		    \
435
-			STR(PTR)"\t4b, 11b\n\t"		    \
436
-			".previous"			    \
437
-		: "=&r" (res)			    	    \
438
-		: "r" (value), "r" (addr), "i" (-EFAULT)    \
439
-		: "memory");                                \
440
-} while(0)
441
-
442
-#define     _StoreDW(addr, value, res) \
443
-do {                                                        \
444
-		__asm__ __volatile__ (                      \
445
-			".set\tpush\n\t"		    \
446
-			".set\tnoat\n\t"		    \
447
-			"1:sb\t%1, 7(%2)\n\t"    	    \
448
-			"dsrl\t$1, %1, 0x8\n\t"		    \
449
-			"2:sb\t$1, 6(%2)\n\t"    	    \
450
-			"dsrl\t$1, $1, 0x8\n\t"		    \
451
-			"3:sb\t$1, 5(%2)\n\t"    	    \
452
-			"dsrl\t$1, $1, 0x8\n\t"		    \
453
-			"4:sb\t$1, 4(%2)\n\t"    	    \
454
-			"dsrl\t$1, $1, 0x8\n\t"		    \
455
-			"5:sb\t$1, 3(%2)\n\t"    	    \
456
-			"dsrl\t$1, $1, 0x8\n\t"		    \
457
-			"6:sb\t$1, 2(%2)\n\t"    	    \
458
-			"dsrl\t$1, $1, 0x8\n\t"		    \
459
-			"7:sb\t$1, 1(%2)\n\t"    	    \
460
-			"dsrl\t$1, $1, 0x8\n\t"		    \
461
-			"8:sb\t$1, 0(%2)\n\t"    	    \
462
-			"dsrl\t$1, $1, 0x8\n\t"		    \
463
-			".set\tpop\n\t"			    \
464
-			"li\t%0, 0\n"			    \
465
-			"10:\n\t"			    \
466
-			".insn\n\t"			    \
467
-			".section\t.fixup,\"ax\"\n\t"	    \
468
-			"11:\tli\t%0, %3\n\t"		    \
469
-			"j\t10b\n\t"			    \
470
-			".previous\n\t"			    \
471
-			".section\t__ex_table,\"a\"\n\t"    \
472
-			STR(PTR)"\t1b, 11b\n\t"		    \
473
-			STR(PTR)"\t2b, 11b\n\t"		    \
474
-			STR(PTR)"\t3b, 11b\n\t"		    \
475
-			STR(PTR)"\t4b, 11b\n\t"		    \
476
-			STR(PTR)"\t5b, 11b\n\t"		    \
477
-			STR(PTR)"\t6b, 11b\n\t"		    \
478
-			STR(PTR)"\t7b, 11b\n\t"		    \
479
-			STR(PTR)"\t8b, 11b\n\t"		    \
480
-			".previous"			    \
481
-		: "=&r" (res)			    	    \
482
-		: "r" (value), "r" (addr), "i" (-EFAULT)    \
483
-		: "memory");                                \
484
-} while(0)
485
-
486
-#endif /* CONFIG_CPU_MIPSR6 */
487
-
488
-#else /* __BIG_ENDIAN */
489
-
490
-#define     _LoadHW(addr, value, res, type)  \
491
-do {                                                        \
492
-		__asm__ __volatile__ (".set\tnoat\n"        \
493
-			"1:\t"type##_lb("%0", "1(%2)")"\n"  \
494
-			"2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
495
-			"sll\t%0, 0x8\n\t"                  \
496
-			"or\t%0, $1\n\t"                    \
497
-			"li\t%1, 0\n"                       \
498
-			"3:\t.set\tat\n\t"                  \
499
-			".insn\n\t"                         \
500
-			".section\t.fixup,\"ax\"\n\t"       \
501
-			"4:\tli\t%1, %3\n\t"                \
502
-			"j\t3b\n\t"                         \
503
-			".previous\n\t"                     \
504
-			".section\t__ex_table,\"a\"\n\t"    \
505
-			STR(PTR)"\t1b, 4b\n\t"              \
506
-			STR(PTR)"\t2b, 4b\n\t"              \
507
-			".previous"                         \
508
-			: "=&r" (value), "=r" (res)         \
509
-			: "r" (addr), "i" (-EFAULT));       \
510
-} while(0)
511
-
512
-#ifndef CONFIG_CPU_MIPSR6
513
-#define     _LoadW(addr, value, res, type)   \
514
-do {                                                        \
515
-		__asm__ __volatile__ (                      \
516
-			"1:\t"type##_lwl("%0", "3(%2)")"\n" \
517
-			"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
518
-			"li\t%1, 0\n"                       \
519
-			"3:\n\t"                            \
520
-			".insn\n\t"                         \
521
-			".section\t.fixup,\"ax\"\n\t"       \
522
-			"4:\tli\t%1, %3\n\t"                \
523
-			"j\t3b\n\t"                         \
524
-			".previous\n\t"                     \
525
-			".section\t__ex_table,\"a\"\n\t"    \
526
-			STR(PTR)"\t1b, 4b\n\t"              \
527
-			STR(PTR)"\t2b, 4b\n\t"              \
528
-			".previous"                         \
529
-			: "=&r" (value), "=r" (res)         \
530
-			: "r" (addr), "i" (-EFAULT));       \
531
-} while(0)
532
-
533
-#else
534
-/* MIPSR6 has no lwl instruction */
535
-#define     _LoadW(addr, value, res, type) \
536
-do {                                                        \
537
-		__asm__ __volatile__ (			    \
538
-			".set\tpush\n"			    \
539
-			".set\tnoat\n\t"		    \
540
-			"1:"type##_lb("%0", "3(%2)")"\n\t"  \
541
-			"2:"type##_lbu("$1", "2(%2)")"\n\t" \
542
-			"sll\t%0, 0x8\n\t"		    \
543
-			"or\t%0, $1\n\t"		    \
544
-			"3:"type##_lbu("$1", "1(%2)")"\n\t" \
545
-			"sll\t%0, 0x8\n\t"		    \
546
-			"or\t%0, $1\n\t"		    \
547
-			"4:"type##_lbu("$1", "0(%2)")"\n\t" \
548
-			"sll\t%0, 0x8\n\t"		    \
549
-			"or\t%0, $1\n\t"		    \
550
-			"li\t%1, 0\n"			    \
551
-			".set\tpop\n"			    \
552
-			"10:\n\t"			    \
553
-			".insn\n\t"			    \
554
-			".section\t.fixup,\"ax\"\n\t"	    \
555
-			"11:\tli\t%1, %3\n\t"		    \
556
-			"j\t10b\n\t"			    \
557
-			".previous\n\t"			    \
558
-			".section\t__ex_table,\"a\"\n\t"    \
559
-			STR(PTR)"\t1b, 11b\n\t"		    \
560
-			STR(PTR)"\t2b, 11b\n\t"		    \
561
-			STR(PTR)"\t3b, 11b\n\t"		    \
562
-			STR(PTR)"\t4b, 11b\n\t"		    \
563
-			".previous"			    \
564
-			: "=&r" (value), "=r" (res)	    \
565
-			: "r" (addr), "i" (-EFAULT));       \
566
-} while(0)
567
-
568
-#endif /* CONFIG_CPU_MIPSR6 */
569
-
570
-
571
-#define     _LoadHWU(addr, value, res, type) \
572
-do {                                                        \
573
-		__asm__ __volatile__ (                      \
574
-			".set\tnoat\n"                      \
575
-			"1:\t"type##_lbu("%0", "1(%2)")"\n" \
576
-			"2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
577
-			"sll\t%0, 0x8\n\t"                  \
578
-			"or\t%0, $1\n\t"                    \
579
-			"li\t%1, 0\n"                       \
580
-			"3:\n\t"                            \
581
-			".insn\n\t"                         \
582
-			".set\tat\n\t"                      \
583
-			".section\t.fixup,\"ax\"\n\t"       \
584
-			"4:\tli\t%1, %3\n\t"                \
585
-			"j\t3b\n\t"                         \
586
-			".previous\n\t"                     \
587
-			".section\t__ex_table,\"a\"\n\t"    \
588
-			STR(PTR)"\t1b, 4b\n\t"              \
589
-			STR(PTR)"\t2b, 4b\n\t"              \
590
-			".previous"                         \
591
-			: "=&r" (value), "=r" (res)         \
592
-			: "r" (addr), "i" (-EFAULT));       \
593
-} while(0)
594
-
595
-#ifndef CONFIG_CPU_MIPSR6
596
-#define     _LoadWU(addr, value, res, type)  \
597
-do {                                                        \
598
-		__asm__ __volatile__ (                      \
599
-			"1:\t"type##_lwl("%0", "3(%2)")"\n" \
600
-			"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
601
-			"dsll\t%0, %0, 32\n\t"              \
602
-			"dsrl\t%0, %0, 32\n\t"              \
603
-			"li\t%1, 0\n"                       \
604
-			"3:\n\t"                            \
605
-			".insn\n\t"                         \
606
-			"\t.section\t.fixup,\"ax\"\n\t"     \
607
-			"4:\tli\t%1, %3\n\t"                \
608
-			"j\t3b\n\t"                         \
609
-			".previous\n\t"                     \
610
-			".section\t__ex_table,\"a\"\n\t"    \
611
-			STR(PTR)"\t1b, 4b\n\t"              \
612
-			STR(PTR)"\t2b, 4b\n\t"              \
613
-			".previous"                         \
614
-			: "=&r" (value), "=r" (res)         \
615
-			: "r" (addr), "i" (-EFAULT));       \
616
-} while(0)
617
-
618
-#define     _LoadDW(addr, value, res)  \
619
-do {                                                        \
620
-		__asm__ __volatile__ (                      \
621
-			"1:\tldl\t%0, 7(%2)\n"              \
622
-			"2:\tldr\t%0, (%2)\n\t"             \
623
-			"li\t%1, 0\n"                       \
624
-			"3:\n\t"                            \
625
-			".insn\n\t"                         \
626
-			"\t.section\t.fixup,\"ax\"\n\t"     \
627
-			"4:\tli\t%1, %3\n\t"                \
628
-			"j\t3b\n\t"                         \
629
-			".previous\n\t"                     \
630
-			".section\t__ex_table,\"a\"\n\t"    \
631
-			STR(PTR)"\t1b, 4b\n\t"              \
632
-			STR(PTR)"\t2b, 4b\n\t"              \
633
-			".previous"                         \
634
-			: "=&r" (value), "=r" (res)         \
635
-			: "r" (addr), "i" (-EFAULT));       \
636
-} while(0)
637
-
638
-#else
639
-/* MIPSR6 has not lwl and ldl instructions */
640
-#define	    _LoadWU(addr, value, res, type) \
641
-do {                                                        \
642
-		__asm__ __volatile__ (			    \
643
-			".set\tpush\n\t"		    \
644
-			".set\tnoat\n\t"		    \
645
-			"1:"type##_lbu("%0", "3(%2)")"\n\t" \
646
-			"2:"type##_lbu("$1", "2(%2)")"\n\t" \
647
-			"sll\t%0, 0x8\n\t"		    \
648
-			"or\t%0, $1\n\t"		    \
649
-			"3:"type##_lbu("$1", "1(%2)")"\n\t" \
650
-			"sll\t%0, 0x8\n\t"		    \
651
-			"or\t%0, $1\n\t"		    \
652
-			"4:"type##_lbu("$1", "0(%2)")"\n\t" \
653
-			"sll\t%0, 0x8\n\t"		    \
654
-			"or\t%0, $1\n\t"		    \
655
-			"li\t%1, 0\n"			    \
656
-			".set\tpop\n"			    \
657
-			"10:\n\t"			    \
658
-			".insn\n\t"			    \
659
-			".section\t.fixup,\"ax\"\n\t"	    \
660
-			"11:\tli\t%1, %3\n\t"		    \
661
-			"j\t10b\n\t"			    \
662
-			".previous\n\t"			    \
663
-			".section\t__ex_table,\"a\"\n\t"    \
664
-			STR(PTR)"\t1b, 11b\n\t"		    \
665
-			STR(PTR)"\t2b, 11b\n\t"		    \
666
-			STR(PTR)"\t3b, 11b\n\t"		    \
667
-			STR(PTR)"\t4b, 11b\n\t"		    \
668
-			".previous"			    \
669
-			: "=&r" (value), "=r" (res)	    \
670
-			: "r" (addr), "i" (-EFAULT));       \
671
-} while(0)
672
-
673
-#define     _LoadDW(addr, value, res)  \
674
-do {                                                        \
675
-		__asm__ __volatile__ (			    \
676
-			".set\tpush\n\t"		    \
677
-			".set\tnoat\n\t"		    \
678
-			"1:lb\t%0, 7(%2)\n\t"    	    \
679
-			"2:lbu\t$1, 6(%2)\n\t"   	    \
680
-			"dsll\t%0, 0x8\n\t"		    \
681
-			"or\t%0, $1\n\t"		    \
682
-			"3:lbu\t$1, 5(%2)\n\t"   	    \
683
-			"dsll\t%0, 0x8\n\t"		    \
684
-			"or\t%0, $1\n\t"		    \
685
-			"4:lbu\t$1, 4(%2)\n\t"   	    \
686
-			"dsll\t%0, 0x8\n\t"		    \
687
-			"or\t%0, $1\n\t"		    \
688
-			"5:lbu\t$1, 3(%2)\n\t"   	    \
689
-			"dsll\t%0, 0x8\n\t"		    \
690
-			"or\t%0, $1\n\t"		    \
691
-			"6:lbu\t$1, 2(%2)\n\t"   	    \
692
-			"dsll\t%0, 0x8\n\t"		    \
693
-			"or\t%0, $1\n\t"		    \
694
-			"7:lbu\t$1, 1(%2)\n\t"   	    \
695
-			"dsll\t%0, 0x8\n\t"		    \
696
-			"or\t%0, $1\n\t"		    \
697
-			"8:lbu\t$1, 0(%2)\n\t"   	    \
698
-			"dsll\t%0, 0x8\n\t"		    \
699
-			"or\t%0, $1\n\t"		    \
700
-			"li\t%1, 0\n"			    \
701
-			".set\tpop\n\t"			    \
702
-			"10:\n\t"			    \
703
-			".insn\n\t"			    \
704
-			".section\t.fixup,\"ax\"\n\t"	    \
705
-			"11:\tli\t%1, %3\n\t"		    \
706
-			"j\t10b\n\t"			    \
707
-			".previous\n\t"			    \
708
-			".section\t__ex_table,\"a\"\n\t"    \
709
-			STR(PTR)"\t1b, 11b\n\t"		    \
710
-			STR(PTR)"\t2b, 11b\n\t"		    \
711
-			STR(PTR)"\t3b, 11b\n\t"		    \
712
-			STR(PTR)"\t4b, 11b\n\t"		    \
713
-			STR(PTR)"\t5b, 11b\n\t"		    \
714
-			STR(PTR)"\t6b, 11b\n\t"		    \
715
-			STR(PTR)"\t7b, 11b\n\t"		    \
716
-			STR(PTR)"\t8b, 11b\n\t"		    \
717
-			".previous"			    \
718
-			: "=&r" (value), "=r" (res)	    \
719
-			: "r" (addr), "i" (-EFAULT));       \
720
-} while(0)
721
-#endif /* CONFIG_CPU_MIPSR6 */
722
-
723
-#define     _StoreHW(addr, value, res, type) \
724
-do {                                                        \
725
-		__asm__ __volatile__ (                      \
726
-			".set\tnoat\n"                      \
727
-			"1:\t"type##_sb("%1", "0(%2)")"\n"  \
728
-			"srl\t$1,%1, 0x8\n"                 \
729
-			"2:\t"type##_sb("$1", "1(%2)")"\n"  \
730
-			".set\tat\n\t"                      \
731
-			"li\t%0, 0\n"                       \
732
-			"3:\n\t"                            \
733
-			".insn\n\t"                         \
734
-			".section\t.fixup,\"ax\"\n\t"       \
735
-			"4:\tli\t%0, %3\n\t"                \
736
-			"j\t3b\n\t"                         \
737
-			".previous\n\t"                     \
738
-			".section\t__ex_table,\"a\"\n\t"    \
739
-			STR(PTR)"\t1b, 4b\n\t"              \
740
-			STR(PTR)"\t2b, 4b\n\t"              \
741
-			".previous"                         \
742
-			: "=r" (res)                        \
743
-			: "r" (value), "r" (addr), "i" (-EFAULT));\
744
-} while(0)
745
-
746
-#ifndef CONFIG_CPU_MIPSR6
747
-#define     _StoreW(addr, value, res, type)  \
748
-do {                                                        \
749
-		__asm__ __volatile__ (                      \
750
-			"1:\t"type##_swl("%1", "3(%2)")"\n" \
751
-			"2:\t"type##_swr("%1", "(%2)")"\n\t"\
752
-			"li\t%0, 0\n"                       \
753
-			"3:\n\t"                            \
754
-			".insn\n\t"                         \
755
-			".section\t.fixup,\"ax\"\n\t"       \
756
-			"4:\tli\t%0, %3\n\t"                \
757
-			"j\t3b\n\t"                         \
758
-			".previous\n\t"                     \
759
-			".section\t__ex_table,\"a\"\n\t"    \
760
-			STR(PTR)"\t1b, 4b\n\t"              \
761
-			STR(PTR)"\t2b, 4b\n\t"              \
762
-			".previous"                         \
763
-		: "=r" (res)                                \
764
-		: "r" (value), "r" (addr), "i" (-EFAULT));  \
765
-} while(0)
766
-
767
-#define     _StoreDW(addr, value, res) \
768
-do {                                                        \
769
-		__asm__ __volatile__ (                      \
770
-			"1:\tsdl\t%1, 7(%2)\n"              \
771
-			"2:\tsdr\t%1, (%2)\n\t"             \
772
-			"li\t%0, 0\n"                       \
773
-			"3:\n\t"                            \
774
-			".insn\n\t"                         \
775
-			".section\t.fixup,\"ax\"\n\t"       \
776
-			"4:\tli\t%0, %3\n\t"                \
777
-			"j\t3b\n\t"                         \
778
-			".previous\n\t"                     \
779
-			".section\t__ex_table,\"a\"\n\t"    \
780
-			STR(PTR)"\t1b, 4b\n\t"              \
781
-			STR(PTR)"\t2b, 4b\n\t"              \
782
-			".previous"                         \
783
-		: "=r" (res)                                \
784
-		: "r" (value), "r" (addr), "i" (-EFAULT));  \
785
-} while(0)
786
-
787
-#else
788
-/* MIPSR6 has no swl and sdl instructions */
789
-#define     _StoreW(addr, value, res, type)  \
790
-do {                                                        \
791
-		__asm__ __volatile__ (                      \
792
-			".set\tpush\n\t"		    \
793
-			".set\tnoat\n\t"		    \
794
-			"1:"type##_sb("%1", "0(%2)")"\n\t"  \
795
-			"srl\t$1, %1, 0x8\n\t"		    \
796
-			"2:"type##_sb("$1", "1(%2)")"\n\t"  \
797
-			"srl\t$1, $1,  0x8\n\t"		    \
798
-			"3:"type##_sb("$1", "2(%2)")"\n\t"  \
799
-			"srl\t$1, $1, 0x8\n\t"		    \
800
-			"4:"type##_sb("$1", "3(%2)")"\n\t"  \
801
-			".set\tpop\n\t"			    \
802
-			"li\t%0, 0\n"			    \
803
-			"10:\n\t"			    \
804
-			".insn\n\t"			    \
805
-			".section\t.fixup,\"ax\"\n\t"	    \
806
-			"11:\tli\t%0, %3\n\t"		    \
807
-			"j\t10b\n\t"			    \
808
-			".previous\n\t"			    \
809
-			".section\t__ex_table,\"a\"\n\t"    \
810
-			STR(PTR)"\t1b, 11b\n\t"		    \
811
-			STR(PTR)"\t2b, 11b\n\t"		    \
812
-			STR(PTR)"\t3b, 11b\n\t"		    \
813
-			STR(PTR)"\t4b, 11b\n\t"		    \
814
-			".previous"			    \
815
-		: "=&r" (res)			    	    \
816
-		: "r" (value), "r" (addr), "i" (-EFAULT)    \
817
-		: "memory");                                \
818
-} while(0)
819
-
820
-#define     _StoreDW(addr, value, res) \
821
-do {                                                        \
822
-		__asm__ __volatile__ (                      \
823
-			".set\tpush\n\t"		    \
824
-			".set\tnoat\n\t"		    \
825
-			"1:sb\t%1, 0(%2)\n\t"    	    \
826
-			"dsrl\t$1, %1, 0x8\n\t"		    \
827
-			"2:sb\t$1, 1(%2)\n\t"    	    \
828
-			"dsrl\t$1, $1, 0x8\n\t"		    \
829
-			"3:sb\t$1, 2(%2)\n\t"    	    \
830
-			"dsrl\t$1, $1, 0x8\n\t"		    \
831
-			"4:sb\t$1, 3(%2)\n\t"    	    \
832
-			"dsrl\t$1, $1, 0x8\n\t"		    \
833
-			"5:sb\t$1, 4(%2)\n\t"    	    \
834
-			"dsrl\t$1, $1, 0x8\n\t"		    \
835
-			"6:sb\t$1, 5(%2)\n\t"    	    \
836
-			"dsrl\t$1, $1, 0x8\n\t"		    \
837
-			"7:sb\t$1, 6(%2)\n\t"    	    \
838
-			"dsrl\t$1, $1, 0x8\n\t"		    \
839
-			"8:sb\t$1, 7(%2)\n\t"    	    \
840
-			"dsrl\t$1, $1, 0x8\n\t"		    \
841
-			".set\tpop\n\t"			    \
842
-			"li\t%0, 0\n"			    \
843
-			"10:\n\t"			    \
844
-			".insn\n\t"			    \
845
-			".section\t.fixup,\"ax\"\n\t"	    \
846
-			"11:\tli\t%0, %3\n\t"		    \
847
-			"j\t10b\n\t"			    \
848
-			".previous\n\t"			    \
849
-			".section\t__ex_table,\"a\"\n\t"    \
850
-			STR(PTR)"\t1b, 11b\n\t"		    \
851
-			STR(PTR)"\t2b, 11b\n\t"		    \
852
-			STR(PTR)"\t3b, 11b\n\t"		    \
853
-			STR(PTR)"\t4b, 11b\n\t"		    \
854
-			STR(PTR)"\t5b, 11b\n\t"		    \
855
-			STR(PTR)"\t6b, 11b\n\t"		    \
856
-			STR(PTR)"\t7b, 11b\n\t"		    \
857
-			STR(PTR)"\t8b, 11b\n\t"		    \
858
-			".previous"			    \
859
-		: "=&r" (res)			    	    \
860
-		: "r" (value), "r" (addr), "i" (-EFAULT)    \
861
-		: "memory");                                \
862
-} while(0)
863
-
864
-#endif /* CONFIG_CPU_MIPSR6 */
865
-#endif
866
-
867
-#define LoadHWU(addr, value, res)	_LoadHWU(addr, value, res, kernel)
868
-#define LoadHWUE(addr, value, res)	_LoadHWU(addr, value, res, user)
869
-#define LoadWU(addr, value, res)	_LoadWU(addr, value, res, kernel)
870
-#define LoadWUE(addr, value, res)	_LoadWU(addr, value, res, user)
871
-#define LoadHW(addr, value, res)	_LoadHW(addr, value, res, kernel)
872
-#define LoadHWE(addr, value, res)	_LoadHW(addr, value, res, user)
873
-#define LoadW(addr, value, res)		_LoadW(addr, value, res, kernel)
874
-#define LoadWE(addr, value, res)	_LoadW(addr, value, res, user)
875
-#define LoadDW(addr, value, res)	_LoadDW(addr, value, res)
876
-
877
-#define StoreHW(addr, value, res)	_StoreHW(addr, value, res, kernel)
878
-#define StoreHWE(addr, value, res)	_StoreHW(addr, value, res, user)
879
-#define StoreW(addr, value, res)	_StoreW(addr, value, res, kernel)
880
-#define StoreWE(addr, value, res)	_StoreW(addr, value, res, user)
881
-#define StoreDW(addr, value, res)	_StoreDW(addr, value, res)
882
-
883
109
 static void emulate_load_store_insn(struct pt_regs *regs,
884
110
 	void __user *addr, unsigned int __user *pc)
885
111
 {
112
+	unsigned long origpc, orig31, value;
886
113
 	union mips_instruction insn;
887
-	unsigned long value;
888
-	unsigned int res, preempted;
889
-	unsigned long origpc;
890
-	unsigned long orig31;
891
-	void __user *fault_addr = NULL;
114
+	unsigned int res;
892
115
 #ifdef	CONFIG_EVA
893
116
 	mm_segment_t seg;
894
117
 #endif
895
-	union fpureg *fpr;
896
-	enum msa_2b_fmt df;
897
-	unsigned int wd;
898
118
 	origpc = (unsigned long)pc;
899
119
 	orig31 = regs->regs[31];
900
120
 
..
..
@@ -943,7 +163,7 @@
943
163
 		if (insn.dsp_format.func == lx_op) {
944
164
 			switch (insn.dsp_format.op) {
945
165
 			case lwx_op:
946
-				if (!access_ok(VERIFY_READ, addr, 4))
166
+				if (!access_ok(addr, 4))
947
167
 					goto sigbus;
948
168
 				LoadW(addr, value, res);
949
169
 				if (res)
..
..
@@ -952,7 +172,7 @@
952
172
 				regs->regs[insn.dsp_format.rd] = value;
953
173
 				break;
954
174
 			case lhx_op:
955
-				if (!access_ok(VERIFY_READ, addr, 2))
175
+				if (!access_ok(addr, 2))
956
176
 					goto sigbus;
957
177
 				LoadHW(addr, value, res);
958
178
 				if (res)
..
..
@@ -971,84 +191,83 @@
971
191
 			 * memory, so we need to "switch" the address limit to
972
192
 			 * user space, so that address check can work properly.
973
193
 			 */
974
-			seg = get_fs();
975
-			set_fs(USER_DS);
194
+			seg = force_uaccess_begin();
976
195
 			switch (insn.spec3_format.func) {
977
196
 			case lhe_op:
978
-				if (!access_ok(VERIFY_READ, addr, 2)) {
979
-					set_fs(seg);
197
+				if (!access_ok(addr, 2)) {
198
+					force_uaccess_end(seg);
980
199
 					goto sigbus;
981
200
 				}
982
201
 				LoadHWE(addr, value, res);
983
202
 				if (res) {
984
-					set_fs(seg);
203
+					force_uaccess_end(seg);
985
204
 					goto fault;
986
205
 				}
987
206
 				compute_return_epc(regs);
988
207
 				regs->regs[insn.spec3_format.rt] = value;
989
208
 				break;
990
209
 			case lwe_op:
991
-				if (!access_ok(VERIFY_READ, addr, 4)) {
992
-					set_fs(seg);
210
+				if (!access_ok(addr, 4)) {
211
+					force_uaccess_end(seg);
993
212
 					goto sigbus;
994
213
 				}
995
214
 				LoadWE(addr, value, res);
996
215
 				if (res) {
997
-					set_fs(seg);
216
+					force_uaccess_end(seg);
998
217
 					goto fault;
999
218
 				}
1000
219
 				compute_return_epc(regs);
1001
220
 				regs->regs[insn.spec3_format.rt] = value;
1002
221
 				break;
1003
222
 			case lhue_op:
1004
-				if (!access_ok(VERIFY_READ, addr, 2)) {
1005
-					set_fs(seg);
223
+				if (!access_ok(addr, 2)) {
224
+					force_uaccess_end(seg);
1006
225
 					goto sigbus;
1007
226
 				}
1008
227
 				LoadHWUE(addr, value, res);
1009
228
 				if (res) {
1010
-					set_fs(seg);
229
+					force_uaccess_end(seg);
1011
230
 					goto fault;
1012
231
 				}
1013
232
 				compute_return_epc(regs);
1014
233
 				regs->regs[insn.spec3_format.rt] = value;
1015
234
 				break;
1016
235
 			case she_op:
1017
-				if (!access_ok(VERIFY_WRITE, addr, 2)) {
1018
-					set_fs(seg);
236
+				if (!access_ok(addr, 2)) {
237
+					force_uaccess_end(seg);
1019
238
 					goto sigbus;
1020
239
 				}
1021
240
 				compute_return_epc(regs);
1022
241
 				value = regs->regs[insn.spec3_format.rt];
1023
242
 				StoreHWE(addr, value, res);
1024
243
 				if (res) {
1025
-					set_fs(seg);
244
+					force_uaccess_end(seg);
1026
245
 					goto fault;
1027
246
 				}
1028
247
 				break;
1029
248
 			case swe_op:
1030
-				if (!access_ok(VERIFY_WRITE, addr, 4)) {
1031
-					set_fs(seg);
249
+				if (!access_ok(addr, 4)) {
250
+					force_uaccess_end(seg);
1032
251
 					goto sigbus;
1033
252
 				}
1034
253
 				compute_return_epc(regs);
1035
254
 				value = regs->regs[insn.spec3_format.rt];
1036
255
 				StoreWE(addr, value, res);
1037
256
 				if (res) {
1038
-					set_fs(seg);
257
+					force_uaccess_end(seg);
1039
258
 					goto fault;
1040
259
 				}
1041
260
 				break;
1042
261
 			default:
1043
-				set_fs(seg);
262
+				force_uaccess_end(seg);
1044
263
 				goto sigill;
1045
264
 			}
1046
-			set_fs(seg);
265
+			force_uaccess_end(seg);
1047
266
 		}
1048
267
 #endif
1049
268
 		break;
1050
269
 	case lh_op:
1051
-		if (!access_ok(VERIFY_READ, addr, 2))
270
+		if (!access_ok(addr, 2))
1052
271
 			goto sigbus;
1053
272
 
1054
273
 		if (IS_ENABLED(CONFIG_EVA)) {
..
..
@@ -1067,7 +286,7 @@
1067
286
 		break;
1068
287
 
1069
288
 	case lw_op:
1070
-		if (!access_ok(VERIFY_READ, addr, 4))
289
+		if (!access_ok(addr, 4))
1071
290
 			goto sigbus;
1072
291
 
1073
292
 		if (IS_ENABLED(CONFIG_EVA)) {
..
..
@@ -1086,7 +305,7 @@
1086
305
 		break;
1087
306
 
1088
307
 	case lhu_op:
1089
-		if (!access_ok(VERIFY_READ, addr, 2))
308
+		if (!access_ok(addr, 2))
1090
309
 			goto sigbus;
1091
310
 
1092
311
 		if (IS_ENABLED(CONFIG_EVA)) {
..
..
@@ -1113,7 +332,7 @@
1113
332
 		 * would blow up, so for now we don't handle unaligned 64-bit
1114
333
 		 * instructions on 32-bit kernels.
1115
334
 		 */
1116
-		if (!access_ok(VERIFY_READ, addr, 4))
335
+		if (!access_ok(addr, 4))
1117
336
 			goto sigbus;
1118
337
 
1119
338
 		LoadWU(addr, value, res);
..
..
@@ -1136,7 +355,7 @@
1136
355
 		 * would blow up, so for now we don't handle unaligned 64-bit
1137
356
 		 * instructions on 32-bit kernels.
1138
357
 		 */
1139
-		if (!access_ok(VERIFY_READ, addr, 8))
358
+		if (!access_ok(addr, 8))
1140
359
 			goto sigbus;
1141
360
 
1142
361
 		LoadDW(addr, value, res);
..
..
@@ -1151,7 +370,7 @@
1151
370
 		goto sigill;
1152
371
 
1153
372
 	case sh_op:
1154
-		if (!access_ok(VERIFY_WRITE, addr, 2))
373
+		if (!access_ok(addr, 2))
1155
374
 			goto sigbus;
1156
375
 
1157
376
 		compute_return_epc(regs);
..
..
@@ -1171,7 +390,7 @@
1171
390
 		break;
1172
391
 
1173
392
 	case sw_op:
1174
-		if (!access_ok(VERIFY_WRITE, addr, 4))
393
+		if (!access_ok(addr, 4))
1175
394
 			goto sigbus;
1176
395
 
1177
396
 		compute_return_epc(regs);
..
..
@@ -1199,7 +418,7 @@
1199
418
 		 * would blow up, so for now we don't handle unaligned 64-bit
1200
419
 		 * instructions on 32-bit kernels.
1201
420
 		 */
1202
-		if (!access_ok(VERIFY_WRITE, addr, 8))
421
+		if (!access_ok(addr, 8))
1203
422
 			goto sigbus;
1204
423
 
1205
424
 		compute_return_epc(regs);
..
..
@@ -1213,15 +432,18 @@
1213
432
 		/* Cannot handle 64-bit instructions in 32-bit kernel */
1214
433
 		goto sigill;
1215
434
 
435
+#ifdef CONFIG_MIPS_FP_SUPPORT
436
+
1216
437
 	case lwc1_op:
1217
438
 	case ldc1_op:
1218
439
 	case swc1_op:
1219
440
 	case sdc1_op:
1220
-	case cop1x_op:
441
+	case cop1x_op: {
442
+		void __user *fault_addr = NULL;
443
+
1221
444
 		die_if_kernel("Unaligned FP access in kernel code", regs);
1222
445
 		BUG_ON(!used_math());
1223
446
 
1224
-		lose_fpu(1);	/* Save FPU state for the emulator. */
1225
447
 		res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
1226
448
 					       &fault_addr);
1227
449
 		own_fpu(1);	/* Restore FPU state. */
..
..
@@ -1232,8 +454,16 @@
1232
454
 		if (res == 0)
1233
455
 			break;
1234
456
 		return;
457
+	}
458
+#endif /* CONFIG_MIPS_FP_SUPPORT */
1235
459
 
1236
-	case msa_op:
460
+#ifdef CONFIG_CPU_HAS_MSA
461
+
462
+	case msa_op: {
463
+		unsigned int wd, preempted;
464
+		enum msa_2b_fmt df;
465
+		union fpureg *fpr;
466
+
1237
467
 		if (!cpu_has_msa)
1238
468
 			goto sigill;
1239
469
 
..
..
@@ -1250,7 +480,7 @@
1250
480
 
1251
481
 		switch (insn.msa_mi10_format.func) {
1252
482
 		case msa_ld_op:
1253
-			if (!access_ok(VERIFY_READ, addr, sizeof(*fpr)))
483
+			if (!access_ok(addr, sizeof(*fpr)))
1254
484
 				goto sigbus;
1255
485
 
1256
486
 			do {
..
..
@@ -1286,7 +516,7 @@
1286
516
 			break;
1287
517
 
1288
518
 		case msa_st_op:
1289
-			if (!access_ok(VERIFY_WRITE, addr, sizeof(*fpr)))
519
+			if (!access_ok(addr, sizeof(*fpr)))
1290
520
 				goto sigbus;
1291
521
 
1292
522
 			/*
..
..
@@ -1310,6 +540,8 @@
1310
540
 
1311
541
 		compute_return_epc(regs);
1312
542
 		break;
543
+	}
544
+#endif /* CONFIG_CPU_HAS_MSA */
1313
545
 
1314
546
 #ifndef CONFIG_CPU_MIPSR6
1315
547
 	/*
..
..
@@ -1358,20 +590,20 @@
1358
590
 		return;
1359
591
 
1360
592
 	die_if_kernel("Unhandled kernel unaligned access", regs);
1361
-	force_sig(SIGSEGV, current);
593
+	force_sig(SIGSEGV);
1362
594
 
1363
595
 	return;
1364
596
 
1365
597
 sigbus:
1366
598
 	die_if_kernel("Unhandled kernel unaligned access", regs);
1367
-	force_sig(SIGBUS, current);
599
+	force_sig(SIGBUS);
1368
600
 
1369
601
 	return;
1370
602
 
1371
603
 sigill:
1372
604
 	die_if_kernel
1373
605
 	    ("Unhandled kernel unaligned access or invalid instruction", regs);
1374
-	force_sig(SIGILL, current);
606
+	force_sig(SIGILL);
1375
607
 }
1376
608
 
1377
609
 /* Recode table from 16-bit register notation to 32-bit GPR. */
..
..
@@ -1394,7 +626,6 @@
1394
626
 	unsigned long origpc, contpc;
1395
627
 	union mips_instruction insn;
1396
628
 	struct mm_decoded_insn mminsn;
1397
-	void __user *fault_addr = NULL;
1398
629
 
1399
630
 	origpc = regs->cp0_epc;
1400
631
 	orig31 = regs->regs[31];
..
..
@@ -1458,7 +689,7 @@
1458
689
 			if (reg == 31)
1459
690
 				goto sigbus;
1460
691
 
1461
-			if (!access_ok(VERIFY_READ, addr, 8))
692
+			if (!access_ok(addr, 8))
1462
693
 				goto sigbus;
1463
694
 
1464
695
 			LoadW(addr, value, res);
..
..
@@ -1477,7 +708,7 @@
1477
708
 			if (reg == 31)
1478
709
 				goto sigbus;
1479
710
 
1480
-			if (!access_ok(VERIFY_WRITE, addr, 8))
711
+			if (!access_ok(addr, 8))
1481
712
 				goto sigbus;
1482
713
 
1483
714
 			value = regs->regs[reg];
..
..
@@ -1497,7 +728,7 @@
1497
728
 			if (reg == 31)
1498
729
 				goto sigbus;
1499
730
 
1500
-			if (!access_ok(VERIFY_READ, addr, 16))
731
+			if (!access_ok(addr, 16))
1501
732
 				goto sigbus;
1502
733
 
1503
734
 			LoadDW(addr, value, res);
..
..
@@ -1520,7 +751,7 @@
1520
751
 			if (reg == 31)
1521
752
 				goto sigbus;
1522
753
 
1523
-			if (!access_ok(VERIFY_WRITE, addr, 16))
754
+			if (!access_ok(addr, 16))
1524
755
 				goto sigbus;
1525
756
 
1526
757
 			value = regs->regs[reg];
..
..
@@ -1543,11 +774,10 @@
1543
774
 			if ((rvar > 9) || !reg)
1544
775
 				goto sigill;
1545
776
 			if (reg & 0x10) {
1546
-				if (!access_ok
1547
-				    (VERIFY_READ, addr, 4 * (rvar + 1)))
777
+				if (!access_ok(addr, 4 * (rvar + 1)))
1548
778
 					goto sigbus;
1549
779
 			} else {
1550
-				if (!access_ok(VERIFY_READ, addr, 4 * rvar))
780
+				if (!access_ok(addr, 4 * rvar))
1551
781
 					goto sigbus;
1552
782
 			}
1553
783
 			if (rvar == 9)
..
..
@@ -1580,11 +810,10 @@
1580
810
 			if ((rvar > 9) || !reg)
1581
811
 				goto sigill;
1582
812
 			if (reg & 0x10) {
1583
-				if (!access_ok
1584
-				    (VERIFY_WRITE, addr, 4 * (rvar + 1)))
813
+				if (!access_ok(addr, 4 * (rvar + 1)))
1585
814
 					goto sigbus;
1586
815
 			} else {
1587
-				if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
816
+				if (!access_ok(addr, 4 * rvar))
1588
817
 					goto sigbus;
1589
818
 			}
1590
819
 			if (rvar == 9)
..
..
@@ -1618,11 +847,10 @@
1618
847
 			if ((rvar > 9) || !reg)
1619
848
 				goto sigill;
1620
849
 			if (reg & 0x10) {
1621
-				if (!access_ok
1622
-				    (VERIFY_READ, addr, 8 * (rvar + 1)))
850
+				if (!access_ok(addr, 8 * (rvar + 1)))
1623
851
 					goto sigbus;
1624
852
 			} else {
1625
-				if (!access_ok(VERIFY_READ, addr, 8 * rvar))
853
+				if (!access_ok(addr, 8 * rvar))
1626
854
 					goto sigbus;
1627
855
 			}
1628
856
 			if (rvar == 9)
..
..
@@ -1660,11 +888,10 @@
1660
888
 			if ((rvar > 9) || !reg)
1661
889
 				goto sigill;
1662
890
 			if (reg & 0x10) {
1663
-				if (!access_ok
1664
-				    (VERIFY_WRITE, addr, 8 * (rvar + 1)))
891
+				if (!access_ok(addr, 8 * (rvar + 1)))
1665
892
 					goto sigbus;
1666
893
 			} else {
1667
-				if (!access_ok(VERIFY_WRITE, addr, 8 * rvar))
894
+				if (!access_ok(addr, 8 * rvar))
1668
895
 					goto sigbus;
1669
896
 			}
1670
897
 			if (rvar == 9)
..
..
@@ -1710,6 +937,7 @@
1710
937
 		/*  LL,SC,LLD,SCD are not serviced */
1711
938
 		goto sigbus;
1712
939
 
940
+#ifdef CONFIG_MIPS_FP_SUPPORT
1713
941
 	case mm_pool32f_op:
1714
942
 		switch (insn.mm_x_format.func) {
1715
943
 		case mm_lwxc1_func:
..
..
@@ -1724,7 +952,9 @@
1724
952
 	case mm_ldc132_op:
1725
953
 	case mm_sdc132_op:
1726
954
 	case mm_lwc132_op:
1727
-	case mm_swc132_op:
955
+	case mm_swc132_op: {
956
+		void __user *fault_addr = NULL;
957
+
1728
958
 fpu_emul:
1729
959
 		/* roll back jump/branch */
1730
960
 		regs->cp0_epc = origpc;
..
..
@@ -1734,7 +964,6 @@
1734
964
 		BUG_ON(!used_math());
1735
965
 		BUG_ON(!is_fpu_owner());
1736
966
 
1737
-		lose_fpu(1);	/* save the FPU state for the emulator */
1738
967
 		res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
1739
968
 					       &fault_addr);
1740
969
 		own_fpu(1);	/* restore FPU state */
..
..
@@ -1745,6 +974,8 @@
1745
974
 		if (res == 0)
1746
975
 			goto success;
1747
976
 		return;
977
+	}
978
+#endif /* CONFIG_MIPS_FP_SUPPORT */
1748
979
 
1749
980
 	case mm_lh32_op:
1750
981
 		reg = insn.mm_i_format.rt;
..
..
@@ -1779,7 +1010,7 @@
1779
1010
 		case mm_lwm16_op:
1780
1011
 			reg = insn.mm16_m_format.rlist;
1781
1012
 			rvar = reg + 1;
1782
-			if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1013
+			if (!access_ok(addr, 4 * rvar))
1783
1014
 				goto sigbus;
1784
1015
 
1785
1016
 			for (i = 16; rvar; rvar--, i++) {
..
..
@@ -1799,7 +1030,7 @@
1799
1030
 		case mm_swm16_op:
1800
1031
 			reg = insn.mm16_m_format.rlist;
1801
1032
 			rvar = reg + 1;
1802
-			if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1033
+			if (!access_ok(addr, 4 * rvar))
1803
1034
 				goto sigbus;
1804
1035
 
1805
1036
 			for (i = 16; rvar; rvar--, i++) {
..
..
@@ -1853,7 +1084,7 @@
1853
1084
 	}
1854
1085
 
1855
1086
 loadHW:
1856
-	if (!access_ok(VERIFY_READ, addr, 2))
1087
+	if (!access_ok(addr, 2))
1857
1088
 		goto sigbus;
1858
1089
 
1859
1090
 	LoadHW(addr, value, res);
..
..
@@ -1863,7 +1094,7 @@
1863
1094
 	goto success;
1864
1095
 
1865
1096
 loadHWU:
1866
-	if (!access_ok(VERIFY_READ, addr, 2))
1097
+	if (!access_ok(addr, 2))
1867
1098
 		goto sigbus;
1868
1099
 
1869
1100
 	LoadHWU(addr, value, res);
..
..
@@ -1873,7 +1104,7 @@
1873
1104
 	goto success;
1874
1105
 
1875
1106
 loadW:
1876
-	if (!access_ok(VERIFY_READ, addr, 4))
1107
+	if (!access_ok(addr, 4))
1877
1108
 		goto sigbus;
1878
1109
 
1879
1110
 	LoadW(addr, value, res);
..
..
@@ -1891,7 +1122,7 @@
1891
1122
 	 * would blow up, so for now we don't handle unaligned 64-bit
1892
1123
 	 * instructions on 32-bit kernels.
1893
1124
 	 */
1894
-	if (!access_ok(VERIFY_READ, addr, 4))
1125
+	if (!access_ok(addr, 4))
1895
1126
 		goto sigbus;
1896
1127
 
1897
1128
 	LoadWU(addr, value, res);
..
..
@@ -1913,7 +1144,7 @@
1913
1144
 	 * would blow up, so for now we don't handle unaligned 64-bit
1914
1145
 	 * instructions on 32-bit kernels.
1915
1146
 	 */
1916
-	if (!access_ok(VERIFY_READ, addr, 8))
1147
+	if (!access_ok(addr, 8))
1917
1148
 		goto sigbus;
1918
1149
 
1919
1150
 	LoadDW(addr, value, res);
..
..
@@ -1927,7 +1158,7 @@
1927
1158
 	goto sigill;
1928
1159
 
1929
1160
 storeHW:
1930
-	if (!access_ok(VERIFY_WRITE, addr, 2))
1161
+	if (!access_ok(addr, 2))
1931
1162
 		goto sigbus;
1932
1163
 
1933
1164
 	value = regs->regs[reg];
..
..
@@ -1937,7 +1168,7 @@
1937
1168
 	goto success;
1938
1169
 
1939
1170
 storeW:
1940
-	if (!access_ok(VERIFY_WRITE, addr, 4))
1171
+	if (!access_ok(addr, 4))
1941
1172
 		goto sigbus;
1942
1173
 
1943
1174
 	value = regs->regs[reg];
..
..
@@ -1955,7 +1186,7 @@
1955
1186
 	 * would blow up, so for now we don't handle unaligned 64-bit
1956
1187
 	 * instructions on 32-bit kernels.
1957
1188
 	 */
1958
-	if (!access_ok(VERIFY_WRITE, addr, 8))
1189
+	if (!access_ok(addr, 8))
1959
1190
 		goto sigbus;
1960
1191
 
1961
1192
 	value = regs->regs[reg];
..
..
@@ -1985,20 +1216,20 @@
1985
1216
 		return;
1986
1217
 
1987
1218
 	die_if_kernel("Unhandled kernel unaligned access", regs);
1988
-	force_sig(SIGSEGV, current);
1219
+	force_sig(SIGSEGV);
1989
1220
 
1990
1221
 	return;
1991
1222
 
1992
1223
 sigbus:
1993
1224
 	die_if_kernel("Unhandled kernel unaligned access", regs);
1994
-	force_sig(SIGBUS, current);
1225
+	force_sig(SIGBUS);
1995
1226
 
1996
1227
 	return;
1997
1228
 
1998
1229
 sigill:
1999
1230
 	die_if_kernel
2000
1231
 	    ("Unhandled kernel unaligned access or invalid instruction", regs);
2001
-	force_sig(SIGILL, current);
1232
+	force_sig(SIGILL);
2002
1233
 }
2003
1234
 
2004
1235
 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
..
..
@@ -2113,7 +1344,7 @@
2113
1344
 		goto sigbus;
2114
1345
 
2115
1346
 	case MIPS16e_lh_op:
2116
-		if (!access_ok(VERIFY_READ, addr, 2))
1347
+		if (!access_ok(addr, 2))
2117
1348
 			goto sigbus;
2118
1349
 
2119
1350
 		LoadHW(addr, value, res);
..
..
@@ -2124,7 +1355,7 @@
2124
1355
 		break;
2125
1356
 
2126
1357
 	case MIPS16e_lhu_op:
2127
-		if (!access_ok(VERIFY_READ, addr, 2))
1358
+		if (!access_ok(addr, 2))
2128
1359
 			goto sigbus;
2129
1360
 
2130
1361
 		LoadHWU(addr, value, res);
..
..
@@ -2137,7 +1368,7 @@
2137
1368
 	case MIPS16e_lw_op:
2138
1369
 	case MIPS16e_lwpc_op:
2139
1370
 	case MIPS16e_lwsp_op:
2140
-		if (!access_ok(VERIFY_READ, addr, 4))
1371
+		if (!access_ok(addr, 4))
2141
1372
 			goto sigbus;
2142
1373
 
2143
1374
 		LoadW(addr, value, res);
..
..
@@ -2156,7 +1387,7 @@
2156
1387
 		 * would blow up, so for now we don't handle unaligned 64-bit
2157
1388
 		 * instructions on 32-bit kernels.
2158
1389
 		 */
2159
-		if (!access_ok(VERIFY_READ, addr, 4))
1390
+		if (!access_ok(addr, 4))
2160
1391
 			goto sigbus;
2161
1392
 
2162
1393
 		LoadWU(addr, value, res);
..
..
@@ -2180,7 +1411,7 @@
2180
1411
 		 * would blow up, so for now we don't handle unaligned 64-bit
2181
1412
 		 * instructions on 32-bit kernels.
2182
1413
 		 */
2183
-		if (!access_ok(VERIFY_READ, addr, 8))
1414
+		if (!access_ok(addr, 8))
2184
1415
 			goto sigbus;
2185
1416
 
2186
1417
 		LoadDW(addr, value, res);
..
..
@@ -2195,7 +1426,7 @@
2195
1426
 		goto sigill;
2196
1427
 
2197
1428
 	case MIPS16e_sh_op:
2198
-		if (!access_ok(VERIFY_WRITE, addr, 2))
1429
+		if (!access_ok(addr, 2))
2199
1430
 			goto sigbus;
2200
1431
 
2201
1432
 		MIPS16e_compute_return_epc(regs, &oldinst);
..
..
@@ -2208,7 +1439,7 @@
2208
1439
 	case MIPS16e_sw_op:
2209
1440
 	case MIPS16e_swsp_op:
2210
1441
 	case MIPS16e_i8_op:	/* actually - MIPS16e_swrasp_func */
2211
-		if (!access_ok(VERIFY_WRITE, addr, 4))
1442
+		if (!access_ok(addr, 4))
2212
1443
 			goto sigbus;
2213
1444
 
2214
1445
 		MIPS16e_compute_return_epc(regs, &oldinst);
..
..
@@ -2228,7 +1459,7 @@
2228
1459
 		 * would blow up, so for now we don't handle unaligned 64-bit
2229
1460
 		 * instructions on 32-bit kernels.
2230
1461
 		 */
2231
-		if (!access_ok(VERIFY_WRITE, addr, 8))
1462
+		if (!access_ok(addr, 8))
2232
1463
 			goto sigbus;
2233
1464
 
2234
1465
 		MIPS16e_compute_return_epc(regs, &oldinst);
..
..
@@ -2265,20 +1496,20 @@
2265
1496
 		return;
2266
1497
 
2267
1498
 	die_if_kernel("Unhandled kernel unaligned access", regs);
2268
-	force_sig(SIGSEGV, current);
1499
+	force_sig(SIGSEGV);
2269
1500
 
2270
1501
 	return;
2271
1502
 
2272
1503
 sigbus:
2273
1504
 	die_if_kernel("Unhandled kernel unaligned access", regs);
2274
-	force_sig(SIGBUS, current);
1505
+	force_sig(SIGBUS);
2275
1506
 
2276
1507
 	return;
2277
1508
 
2278
1509
 sigill:
2279
1510
 	die_if_kernel
2280
1511
 	    ("Unhandled kernel unaligned access or invalid instruction", regs);
2281
-	force_sig(SIGILL, current);
1512
+	force_sig(SIGILL);
2282
1513
 }
2283
1514
 
2284
1515
 asmlinkage void do_ade(struct pt_regs *regs)
..
..
@@ -2339,7 +1570,7 @@
2339
1570
 			set_fs(seg);
2340
1571
 
2341
1572
 			return;
2342
-	}
1573
+		}
2343
1574
 
2344
1575
 		goto sigbus;
2345
1576
 	}
..
..
@@ -2358,7 +1589,7 @@
2358
1589
 
2359
1590
 sigbus:
2360
1591
 	die_if_kernel("Kernel unaligned instruction access", regs);
2361
-	force_sig(SIGBUS, current);
1592
+	force_sig(SIGBUS);
2362
1593
 
2363
1594
 	/*
2364
1595
 	 * XXX On return from the signal handler we should advance the epc
..
..
@@ -2369,18 +1600,10 @@
2369
1600
 #ifdef CONFIG_DEBUG_FS
2370
1601
 static int __init debugfs_unaligned(void)
2371
1602
 {
2372
-	struct dentry *d;
2373
-
2374
-	if (!mips_debugfs_dir)
2375
-		return -ENODEV;
2376
-	d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
2377
-			       mips_debugfs_dir, &unaligned_instructions);
2378
-	if (!d)
2379
-		return -ENOMEM;
2380
-	d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
2381
-			       mips_debugfs_dir, &unaligned_action);
2382
-	if (!d)
2383
-		return -ENOMEM;
1603
+	debugfs_create_u32("unaligned_instructions", S_IRUGO, mips_debugfs_dir,
1604
+			   &unaligned_instructions);
1605
+	debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
1606
+			   mips_debugfs_dir, &unaligned_action);
2384
1607
 	return 0;
2385
1608
 }
2386
1609
 arch_initcall(debugfs_unaligned);