update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/mips/kernel/syscall.c
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@@ -37,6 +37,7 @@
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 #include <asm/signal.h>
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 #include <asm/sim.h>
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 #include <asm/shmparam.h>
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+#include <asm/sync.h>
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 #include <asm/sysmips.h>
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 #include <asm/switch_to.h>
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@@ -80,6 +81,7 @@
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 save_static_function(sys_fork);
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 save_static_function(sys_clone);
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+save_static_function(sys_clone3);
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 SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
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 {
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@@ -101,11 +103,12 @@
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 	if (unlikely(addr & 3))
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 		return -EINVAL;
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-	if (unlikely(!access_ok(VERIFY_WRITE, (const void __user *)addr, 4)))
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+	if (unlikely(!access_ok((const void __user *)addr, 4)))
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 		return -EINVAL;
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-	if (cpu_has_llsc && R10000_LLSC_WAR) {
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+	if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
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 		__asm__ __volatile__ (
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+		"	.set	push					\n"
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 		"	.set	arch=r4000				\n"
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 		"	li	%[err], 0				\n"
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 		"1:	ll	%[old], (%[addr])			\n"
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@@ -122,7 +125,7 @@
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 		"	"STR(PTR)"	1b, 4b				\n"
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 		"	"STR(PTR)"	2b, 4b				\n"
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 		"	.previous					\n"
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-		"	.set	mips0					\n"
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+		"	.set	pop					\n"
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 		: [old] "=&r" (old),
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 		  [err] "=&r" (err),
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 		  [tmp] "=&r" (tmp)
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@@ -132,9 +135,11 @@
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 		: "memory");
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 	} else if (cpu_has_llsc) {
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 		__asm__ __volatile__ (
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+		"	.set	push					\n"
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 		"	.set	"MIPS_ISA_ARCH_LEVEL"			\n"
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 		"	li	%[err], 0				\n"
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 		"1:							\n"
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+		"	" __SYNC(full, loongson3_war) "			\n"
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 		user_ll("%[old]", "(%[addr])")
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 		"	move	%[tmp], %[new]				\n"
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 		"2:							\n"
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@@ -150,7 +155,7 @@
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 		"	"STR(PTR)"	1b, 5b				\n"
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 		"	"STR(PTR)"	2b, 5b				\n"
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 		"	.previous					\n"
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-		"	.set	mips0					\n"
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+		"	.set	pop					\n"
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 		: [old] "=&r" (old),
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 		  [err] "=&r" (err),
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 		  [tmp] "=&r" (tmp)