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hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/arch/mips/kernel/r4k_fpu.S
....@@ -41,7 +41,7 @@
4141 LEAF(_save_fp)
4242 EXPORT_SYMBOL(_save_fp)
4343 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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-		defined(CONFIG_CPU_MIPSR6)
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+    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
4545 	mfc0	t0, CP0_STATUS
4646 #endif
4747 	fpu_save_double a0 t0 t1		# clobbers t1
....@@ -53,7 +53,7 @@
5353  */
5454 LEAF(_restore_fp)
5555 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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-		defined(CONFIG_CPU_MIPSR6)
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+    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
5757 	mfc0	t0, CP0_STATUS
5858 #endif
5959 	fpu_restore_double a0 t0 t1		# clobbers t1
....@@ -86,150 +86,6 @@
8686 
8787 #endif
8888 
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-/*
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- * Load the FPU with signalling NANS.  This bit pattern we're using has
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- * the property that no matter whether considered as single or as double
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- * precision represents signaling NANS.
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- *
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- * The value to initialize fcr31 to comes in $a0.
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- */
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-
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-	.set push
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-	SET_HARDFLOAT
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-
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-LEAF(_init_fpu)
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-	mfc0	t0, CP0_STATUS
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-	li	t1, ST0_CU1
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-	or	t0, t1
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-	mtc0	t0, CP0_STATUS
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-	enable_fpu_hazard
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-
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-	ctc1	a0, fcr31
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-
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-	li	t1, -1				# SNaN
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-
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-#ifdef CONFIG_64BIT
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-	sll	t0, t0, 5
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-	bgez	t0, 1f				# 16 / 32 register mode?
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-
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-	dmtc1	t1, $f1
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-	dmtc1	t1, $f3
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-	dmtc1	t1, $f5
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-	dmtc1	t1, $f7
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-	dmtc1	t1, $f9
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-	dmtc1	t1, $f11
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-	dmtc1	t1, $f13
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-	dmtc1	t1, $f15
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-	dmtc1	t1, $f17
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-	dmtc1	t1, $f19
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-	dmtc1	t1, $f21
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-	dmtc1	t1, $f23
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-	dmtc1	t1, $f25
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-	dmtc1	t1, $f27
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-	dmtc1	t1, $f29
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-	dmtc1	t1, $f31
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-1:
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-#endif
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-
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-#ifdef CONFIG_CPU_MIPS32
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-	mtc1	t1, $f0
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-	mtc1	t1, $f1
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-	mtc1	t1, $f2
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-	mtc1	t1, $f3
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-	mtc1	t1, $f4
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-	mtc1	t1, $f5
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-	mtc1	t1, $f6
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-	mtc1	t1, $f7
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-	mtc1	t1, $f8
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-	mtc1	t1, $f9
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-	mtc1	t1, $f10
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-	mtc1	t1, $f11
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-	mtc1	t1, $f12
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-	mtc1	t1, $f13
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-	mtc1	t1, $f14
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-	mtc1	t1, $f15
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-	mtc1	t1, $f16
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-	mtc1	t1, $f17
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-	mtc1	t1, $f18
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-	mtc1	t1, $f19
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-	mtc1	t1, $f20
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-	mtc1	t1, $f21
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-	mtc1	t1, $f22
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-	mtc1	t1, $f23
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-	mtc1	t1, $f24
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-	mtc1	t1, $f25
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-	mtc1	t1, $f26
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-	mtc1	t1, $f27
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-	mtc1	t1, $f28
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-	mtc1	t1, $f29
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-	mtc1	t1, $f30
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-	mtc1	t1, $f31
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-
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-#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)
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-	.set    push
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-	.set    MIPS_ISA_LEVEL_RAW
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-	.set	fp=64
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-	sll     t0, t0, 5			# is Status.FR set?
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-	bgez    t0, 1f				# no: skip setting upper 32b
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-
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-	mthc1   t1, $f0
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-	mthc1   t1, $f1
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-	mthc1   t1, $f2
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-	mthc1   t1, $f3
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-	mthc1   t1, $f4
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-	mthc1   t1, $f5
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-	mthc1   t1, $f6
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-	mthc1   t1, $f7
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-	mthc1   t1, $f8
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-	mthc1   t1, $f9
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-	mthc1   t1, $f10
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-	mthc1   t1, $f11
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-	mthc1   t1, $f12
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-	mthc1   t1, $f13
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-	mthc1   t1, $f14
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-	mthc1   t1, $f15
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-	mthc1   t1, $f16
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-	mthc1   t1, $f17
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-	mthc1   t1, $f18
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-	mthc1   t1, $f19
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-	mthc1   t1, $f20
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-	mthc1   t1, $f21
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-	mthc1   t1, $f22
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-	mthc1   t1, $f23
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-	mthc1   t1, $f24
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-	mthc1   t1, $f25
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-	mthc1   t1, $f26
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-	mthc1   t1, $f27
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-	mthc1   t1, $f28
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-	mthc1   t1, $f29
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-	mthc1   t1, $f30
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-	mthc1   t1, $f31
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-1:	.set    pop
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-#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */
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-#else
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-	.set	MIPS_ISA_ARCH_LEVEL_RAW
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-	dmtc1	t1, $f0
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-	dmtc1	t1, $f2
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-	dmtc1	t1, $f4
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-	dmtc1	t1, $f6
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-	dmtc1	t1, $f8
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-	dmtc1	t1, $f10
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-	dmtc1	t1, $f12
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-	dmtc1	t1, $f14
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-	dmtc1	t1, $f16
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-	dmtc1	t1, $f18
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-	dmtc1	t1, $f20
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-	dmtc1	t1, $f22
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-	dmtc1	t1, $f24
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-	dmtc1	t1, $f26
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-	dmtc1	t1, $f28
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-	dmtc1	t1, $f30
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-#endif
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-	jr	ra
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-	END(_init_fpu)
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-
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-	.set pop	/* SET_HARDFLOAT */
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-
23389 	.set	noreorder
23490 
23591 /**
....@@ -247,10 +103,10 @@
247103 	.set	pop
248104 
249105 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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-		defined(CONFIG_CPU_MIPSR6)
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+    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
251107 	.set	push
252108 	SET_HARDFLOAT
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-#ifdef CONFIG_CPU_MIPSR2
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+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5)
254110 	.set	mips32r2
255111 	.set	fp=64
256112 	mfc0	t0, CP0_STATUS
....@@ -314,11 +170,11 @@
314170 LEAF(_restore_fp_context)
315171 	EX	lw t1, 0(a1)
316172 
317
-#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2)  || \
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-		defined(CONFIG_CPU_MIPSR6)
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+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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+    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
319175 	.set	push
320176 	SET_HARDFLOAT
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-#ifdef CONFIG_CPU_MIPSR2
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+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5)
322178 	.set	mips32r2
323179 	.set	fp=64
324180 	mfc0	t0, CP0_STATUS