update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/mips/kernel/pm-cps.c
..
..
@@ -1,11 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
1
2
 /*
2
3
  * Copyright (C) 2014 Imagination Technologies
3
4
  * Author: Paul Burton <paul.burton@mips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of the GNU General Public License as published by the
7
- * Free Software Foundation;  either version 2 of the  License, or (at your
8
- * option) any later version.
9
5
  */
10
6
 
11
7
 #include <linux/cpuhotplug.h>
..
..
@@ -311,7 +307,7 @@
311
307
 	}
312
308
 
313
309
 	/* Barrier ensuring previous cache invalidates are complete */
314
-	uasm_i_sync(pp, STYPE_SYNC);
310
+	uasm_i_sync(pp, __SYNC_full);
315
311
 	uasm_i_ehb(pp);
316
312
 
317
313
 	/* Check whether the pipeline stalled due to the FSB being full */
..
..
@@ -401,7 +397,7 @@
401
397
 
402
398
 	if (coupled_coherence) {
403
399
 		/* Increment ready_count */
404
-		uasm_i_sync(&p, STYPE_SYNC_MB);
400
+		uasm_i_sync(&p, __SYNC_mb);
405
401
 		uasm_build_label(&l, p, lbl_incready);
406
402
 		uasm_i_ll(&p, t1, 0, r_nc_count);
407
403
 		uasm_i_addiu(&p, t2, t1, 1);
..
..
@@ -410,7 +406,7 @@
410
406
 		uasm_i_addiu(&p, t1, t1, 1);
411
407
 
412
408
 		/* Barrier ensuring all CPUs see the updated r_nc_count value */
413
-		uasm_i_sync(&p, STYPE_SYNC_MB);
409
+		uasm_i_sync(&p, __SYNC_mb);
414
410
 
415
411
 		/*
416
412
 		 * If this is the last VPE to become ready for non-coherence
..
..
@@ -477,7 +473,7 @@
477
473
 			      Index_Writeback_Inv_D, lbl_flushdcache);
478
474
 
479
475
 	/* Barrier ensuring previous cache invalidates are complete */
480
-	uasm_i_sync(&p, STYPE_SYNC);
476
+	uasm_i_sync(&p, __SYNC_full);
481
477
 	uasm_i_ehb(&p);
482
478
 
483
479
 	if (mips_cm_revision() < CM_REV_CM3) {
..
..
@@ -491,7 +487,7 @@
491
487
 		uasm_i_lw(&p, t0, 0, r_pcohctl);
492
488
 
493
489
 		/* Barrier to ensure write to coherence control is complete */
494
-		uasm_i_sync(&p, STYPE_SYNC);
490
+		uasm_i_sync(&p, __SYNC_full);
495
491
 		uasm_i_ehb(&p);
496
492
 	}
497
493
 
..
..
@@ -538,7 +534,7 @@
538
534
 		}
539
535
 
540
536
 		/* Barrier to ensure write to CPC command is complete */
541
-		uasm_i_sync(&p, STYPE_SYNC);
537
+		uasm_i_sync(&p, __SYNC_full);
542
538
 		uasm_i_ehb(&p);
543
539
 	}
544
540
 
..
..
@@ -576,13 +572,13 @@
576
572
 	uasm_i_lw(&p, t0, 0, r_pcohctl);
577
573
 
578
574
 	/* Barrier to ensure write to coherence control is complete */
579
-	uasm_i_sync(&p, STYPE_SYNC);
575
+	uasm_i_sync(&p, __SYNC_full);
580
576
 	uasm_i_ehb(&p);
581
577
 
582
578
 	if (coupled_coherence && (state == CPS_PM_NC_WAIT)) {
583
579
 		/* Decrement ready_count */
584
580
 		uasm_build_label(&l, p, lbl_decready);
585
-		uasm_i_sync(&p, STYPE_SYNC_MB);
581
+		uasm_i_sync(&p, __SYNC_mb);
586
582
 		uasm_i_ll(&p, t1, 0, r_nc_count);
587
583
 		uasm_i_addiu(&p, t2, t1, -1);
588
584
 		uasm_i_sc(&p, t2, 0, r_nc_count);
..
..
@@ -590,7 +586,7 @@
590
586
 		uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
591
587
 
592
588
 		/* Barrier ensuring all CPUs see the updated r_nc_count value */
593
-		uasm_i_sync(&p, STYPE_SYNC_MB);
589
+		uasm_i_sync(&p, __SYNC_mb);
594
590
 	}
595
591
 
596
592
 	if (coupled_coherence && (state == CPS_PM_CLOCK_GATED)) {
..
..
@@ -612,7 +608,7 @@
612
608
 		uasm_build_label(&l, p, lbl_secondary_cont);
613
609
 
614
610
 		/* Barrier ensuring all CPUs see the updated r_nc_count value */
615
-		uasm_i_sync(&p, STYPE_SYNC_MB);
611
+		uasm_i_sync(&p, __SYNC_mb);
616
612
 	}
617
613
 
618
614
 	/* The core is coherent, time to return to C code */