update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/mips/kernel/mips-r2-to-r6-emul.c
..
..
@@ -1109,7 +1109,7 @@
1109
1109
 			err = SIGILL;
1110
1110
 			break;
1111
1111
 		}
1112
-		/* fall through */
1112
+		fallthrough;
1113
1113
 	case beql_op:
1114
1114
 	case bnel_op:
1115
1115
 		if (delay_slot(regs)) {
..
..
@@ -1174,13 +1174,6 @@
1174
1174
 fpu_emul:
1175
1175
 		regs->regs[31] = r31;
1176
1176
 		regs->cp0_epc = epc;
1177
-		if (!used_math()) {     /* First time FPU user.  */
1178
-			preempt_disable();
1179
-			err = init_fpu();
1180
-			preempt_enable();
1181
-			set_used_math();
1182
-		}
1183
-		lose_fpu(1);    /* Save FPU state for the emulator. */
1184
1177
 
1185
1178
 		err = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1186
1179
 					       &fault_addr);
..
..
@@ -1212,7 +1205,7 @@
1212
1205
 	case lwl_op:
1213
1206
 		rt = regs->regs[MIPSInst_RT(inst)];
1214
1207
 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1215
-		if (!access_ok(VERIFY_READ, (void __user *)vaddr, 4)) {
1208
+		if (!access_ok((void __user *)vaddr, 4)) {
1216
1209
 			current->thread.cp0_baduaddr = vaddr;
1217
1210
 			err = SIGSEGV;
1218
1211
 			break;
..
..
@@ -1285,7 +1278,7 @@
1285
1278
 	case lwr_op:
1286
1279
 		rt = regs->regs[MIPSInst_RT(inst)];
1287
1280
 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1288
-		if (!access_ok(VERIFY_READ, (void __user *)vaddr, 4)) {
1281
+		if (!access_ok((void __user *)vaddr, 4)) {
1289
1282
 			current->thread.cp0_baduaddr = vaddr;
1290
1283
 			err = SIGSEGV;
1291
1284
 			break;
..
..
@@ -1359,7 +1352,7 @@
1359
1352
 	case swl_op:
1360
1353
 		rt = regs->regs[MIPSInst_RT(inst)];
1361
1354
 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1362
-		if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 4)) {
1355
+		if (!access_ok((void __user *)vaddr, 4)) {
1363
1356
 			current->thread.cp0_baduaddr = vaddr;
1364
1357
 			err = SIGSEGV;
1365
1358
 			break;
..
..
@@ -1429,7 +1422,7 @@
1429
1422
 	case swr_op:
1430
1423
 		rt = regs->regs[MIPSInst_RT(inst)];
1431
1424
 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1432
-		if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 4)) {
1425
+		if (!access_ok((void __user *)vaddr, 4)) {
1433
1426
 			current->thread.cp0_baduaddr = vaddr;
1434
1427
 			err = SIGSEGV;
1435
1428
 			break;
..
..
@@ -1504,7 +1497,7 @@
1504
1497
 
1505
1498
 		rt = regs->regs[MIPSInst_RT(inst)];
1506
1499
 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1507
-		if (!access_ok(VERIFY_READ, (void __user *)vaddr, 8)) {
1500
+		if (!access_ok((void __user *)vaddr, 8)) {
1508
1501
 			current->thread.cp0_baduaddr = vaddr;
1509
1502
 			err = SIGSEGV;
1510
1503
 			break;
..
..
@@ -1623,7 +1616,7 @@
1623
1616
 
1624
1617
 		rt = regs->regs[MIPSInst_RT(inst)];
1625
1618
 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1626
-		if (!access_ok(VERIFY_READ, (void __user *)vaddr, 8)) {
1619
+		if (!access_ok((void __user *)vaddr, 8)) {
1627
1620
 			current->thread.cp0_baduaddr = vaddr;
1628
1621
 			err = SIGSEGV;
1629
1622
 			break;
..
..
@@ -1742,7 +1735,7 @@
1742
1735
 
1743
1736
 		rt = regs->regs[MIPSInst_RT(inst)];
1744
1737
 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1745
-		if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 8)) {
1738
+		if (!access_ok((void __user *)vaddr, 8)) {
1746
1739
 			current->thread.cp0_baduaddr = vaddr;
1747
1740
 			err = SIGSEGV;
1748
1741
 			break;
..
..
@@ -1860,7 +1853,7 @@
1860
1853
 
1861
1854
 		rt = regs->regs[MIPSInst_RT(inst)];
1862
1855
 		vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst);
1863
-		if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 8)) {
1856
+		if (!access_ok((void __user *)vaddr, 8)) {
1864
1857
 			current->thread.cp0_baduaddr = vaddr;
1865
1858
 			err = SIGSEGV;
1866
1859
 			break;
..
..
@@ -1977,7 +1970,7 @@
1977
1970
 			err = SIGBUS;
1978
1971
 			break;
1979
1972
 		}
1980
-		if (!access_ok(VERIFY_READ, (void __user *)vaddr, 4)) {
1973
+		if (!access_ok((void __user *)vaddr, 4)) {
1981
1974
 			current->thread.cp0_baduaddr = vaddr;
1982
1975
 			err = SIGBUS;
1983
1976
 			break;
..
..
@@ -2033,7 +2026,7 @@
2033
2026
 			err = SIGBUS;
2034
2027
 			break;
2035
2028
 		}
2036
-		if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 4)) {
2029
+		if (!access_ok((void __user *)vaddr, 4)) {
2037
2030
 			current->thread.cp0_baduaddr = vaddr;
2038
2031
 			err = SIGBUS;
2039
2032
 			break;
..
..
@@ -2096,7 +2089,7 @@
2096
2089
 			err = SIGBUS;
2097
2090
 			break;
2098
2091
 		}
2099
-		if (!access_ok(VERIFY_READ, (void __user *)vaddr, 8)) {
2092
+		if (!access_ok((void __user *)vaddr, 8)) {
2100
2093
 			current->thread.cp0_baduaddr = vaddr;
2101
2094
 			err = SIGBUS;
2102
2095
 			break;
..
..
@@ -2157,7 +2150,7 @@
2157
2150
 			err = SIGBUS;
2158
2151
 			break;
2159
2152
 		}
2160
-		if (!access_ok(VERIFY_WRITE, (void __user *)vaddr, 8)) {
2153
+		if (!access_ok((void __user *)vaddr, 8)) {
2161
2154
 			current->thread.cp0_baduaddr = vaddr;
2162
2155
 			err = SIGBUS;
2163
2156
 			break;
..
..
@@ -2242,7 +2235,7 @@
2242
2235
 
2243
2236
 #ifdef CONFIG_DEBUG_FS
2244
2237
 
2245
-static int mipsr2_stats_show(struct seq_file *s, void *unused)
2238
+static int mipsr2_emul_show(struct seq_file *s, void *unused)
2246
2239
 {
2247
2240
 
2248
2241
 	seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n");
..
..
@@ -2308,9 +2301,9 @@
2308
2301
 	return 0;
2309
2302
 }
2310
2303
 
2311
-static int mipsr2_stats_clear_show(struct seq_file *s, void *unused)
2304
+static int mipsr2_clear_show(struct seq_file *s, void *unused)
2312
2305
 {
2313
-	mipsr2_stats_show(s, unused);
2306
+	mipsr2_emul_show(s, unused);
2314
2307
 
2315
2308
 	__this_cpu_write((mipsr2emustats).movs, 0);
2316
2309
 	__this_cpu_write((mipsr2bdemustats).movs, 0);
..
..
@@ -2353,50 +2346,15 @@
2353
2346
 	return 0;
2354
2347
 }
2355
2348
 
2356
-static int mipsr2_stats_open(struct inode *inode, struct file *file)
2357
-{
2358
-	return single_open(file, mipsr2_stats_show, inode->i_private);
2359
-}
2360
-
2361
-static int mipsr2_stats_clear_open(struct inode *inode, struct file *file)
2362
-{
2363
-	return single_open(file, mipsr2_stats_clear_show, inode->i_private);
2364
-}
2365
-
2366
-static const struct file_operations mipsr2_emul_fops = {
2367
-	.open                   = mipsr2_stats_open,
2368
-	.read			= seq_read,
2369
-	.llseek			= seq_lseek,
2370
-	.release		= single_release,
2371
-};
2372
-
2373
-static const struct file_operations mipsr2_clear_fops = {
2374
-	.open                   = mipsr2_stats_clear_open,
2375
-	.read			= seq_read,
2376
-	.llseek			= seq_lseek,
2377
-	.release		= single_release,
2378
-};
2379
-
2349
+DEFINE_SHOW_ATTRIBUTE(mipsr2_emul);
2350
+DEFINE_SHOW_ATTRIBUTE(mipsr2_clear);
2380
2351
 
2381
2352
 static int __init mipsr2_init_debugfs(void)
2382
2353
 {
2383
-	struct dentry		*mipsr2_emul;
2384
-
2385
-	if (!mips_debugfs_dir)
2386
-		return -ENODEV;
2387
-
2388
-	mipsr2_emul = debugfs_create_file("r2_emul_stats", S_IRUGO,
2389
-					  mips_debugfs_dir, NULL,
2390
-					  &mipsr2_emul_fops);
2391
-	if (!mipsr2_emul)
2392
-		return -ENOMEM;
2393
-
2394
-	mipsr2_emul = debugfs_create_file("r2_emul_stats_clear", S_IRUGO,
2395
-					  mips_debugfs_dir, NULL,
2396
-					  &mipsr2_clear_fops);
2397
-	if (!mipsr2_emul)
2398
-		return -ENOMEM;
2399
-
2354
+	debugfs_create_file("r2_emul_stats", S_IRUGO, mips_debugfs_dir, NULL,
2355
+			    &mipsr2_emul_fops);
2356
+	debugfs_create_file("r2_emul_stats_clear", S_IRUGO, mips_debugfs_dir,
2357
+			    NULL, &mipsr2_clear_fops);
2400
2358
 	return 0;
2401
2359
 }
2402
2360