update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/mips/kernel/mips-cm.c
..
..
@@ -1,11 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright (C) 2013 Imagination Technologies
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  * Author: Paul Burton <paul.burton@mips.com>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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  */
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 #include <linux/errno.h>
..
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@@ -118,6 +114,48 @@
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 	"Exclusive/OK", "Exclusive/Data"
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 };
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+static char *cm2_l2_type[4] = {
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+	[0x0] = "None",
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+	[0x1] = "Tag RAM single/double ECC error",
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+	[0x2] = "Data RAM single/double ECC error",
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+	[0x3] = "WS RAM uncorrectable dirty parity"
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+};
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+
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+static char *cm2_l2_instr[32] = {
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+	[0x00] = "L2_NOP",
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+	[0x01] = "L2_ERR_CORR",
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+	[0x02] = "L2_TAG_INV",
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+	[0x03] = "L2_WS_CLEAN",
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+	[0x04] = "L2_RD_MDYFY_WR",
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+	[0x05] = "L2_WS_MRU",
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+	[0x06] = "L2_EVICT_LN2",
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+	[0x07] = "0x07",
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+	[0x08] = "L2_EVICT",
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+	[0x09] = "L2_REFL",
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+	[0x0a] = "L2_RD",
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+	[0x0b] = "L2_WR",
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+	[0x0c] = "L2_EVICT_MRU",
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+	[0x0d] = "L2_SYNC",
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+	[0x0e] = "L2_REFL_ERR",
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+	[0x0f] = "0x0f",
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+	[0x10] = "L2_INDX_WB_INV",
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+	[0x11] = "L2_INDX_LD_TAG",
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+	[0x12] = "L2_INDX_ST_TAG",
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+	[0x13] = "L2_INDX_ST_DATA",
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+	[0x14] = "L2_INDX_ST_ECC",
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+	[0x15] = "0x15",
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+	[0x16] = "0x16",
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+	[0x17] = "0x17",
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+	[0x18] = "L2_FTCH_AND_LCK",
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+	[0x19] = "L2_HIT_INV",
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+	[0x1a] = "L2_HIT_WB_INV",
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+	[0x1b] = "L2_HIT_WB",
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+	[0x1c] = "0x1c",
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+	[0x1d] = "0x1d",
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+	[0x1e] = "0x1e",
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+	[0x1f] = "0x1f"
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+};
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+
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 static char *cm2_causes[32] = {
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 	"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
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 	"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
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..
@@ -125,7 +163,7 @@
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 	"0x0c", "0x0d", "0x0e", "0x0f",
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 	"0x10", "INTVN_WR_ERR", "INTVN_RD_ERR", "0x13",
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 	"0x14", "0x15", "0x16", "0x17",
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-	"0x18", "0x19", "0x1a", "0x1b",
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+	"L2_RD_UNCORR", "L2_WR_UNCORR", "L2_CORR", "0x1b",
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 	"0x1c", "0x1d", "0x1e", "0x1f"
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 };
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..
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@@ -197,7 +235,7 @@
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 	write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN);
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 	/* Map the region */
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-	mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
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+	mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE);
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 }
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 int mips_cm_probe(void)
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@@ -218,7 +256,7 @@
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 	if (!addr)
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 		return -ENODEV;
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-	mips_gcr_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
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+	mips_gcr_base = ioremap(addr, MIPS_CM_GCR_SIZE);
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 	if (!mips_gcr_base)
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 		return -ENXIO;
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..
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@@ -363,7 +401,7 @@
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 				 "CCA=%lu TR=%s MCmd=%s STag=%lu "
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 				 "SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
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 				 cm2_cmd[cmd_bits], stag_bits, sport_bits);
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-		} else {
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+		} else if (cause < 24) {
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 			/* glob state & sresp together */
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 			unsigned long c3_bits = (cm_error >> 18) & 7;
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 			unsigned long c2_bits = (cm_error >> 15) & 7;
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@@ -380,9 +418,25 @@
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 				 cm2_core[c1_bits], cm2_core[c0_bits],
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 				 sc_bit ? "True" : "False",
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 				 cm2_cmd[cmd_bits], sport_bits);
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+		} else {
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+			unsigned long muc_bit = (cm_error >> 23) & 1;
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+			unsigned long ins_bits = (cm_error >> 18) & 0x1f;
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+			unsigned long arr_bits = (cm_error >> 16) & 3;
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+			unsigned long dw_bits = (cm_error >> 12) & 15;
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+			unsigned long way_bits = (cm_error >> 9) & 7;
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+			unsigned long mway_bit = (cm_error >> 8) & 1;
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+			unsigned long syn_bits = (cm_error >> 0) & 0xFF;
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+
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+			snprintf(buf, sizeof(buf),
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+				 "Type=%s%s Instr=%s DW=%lu Way=%lu "
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+				 "MWay=%s Syndrome=0x%02lx",
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+				 muc_bit ? "Multi-UC " : "",
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+				 cm2_l2_type[arr_bits],
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+				 cm2_l2_instr[ins_bits], dw_bits, way_bits,
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+				 mway_bit ? "True" : "False", syn_bits);
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 		}
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-			pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
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-			       cm2_causes[cause], buf);
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+		pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
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+		       cm2_causes[cause], buf);
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 		pr_err("CM_ADDR =%08llx\n", cm_addr);
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 		pr_err("CM_OTHER=%08llx %s\n", cm_other, cm2_causes[ocause]);
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 	} else { /* CM3 */